SAF-XC878-13FFI 5V AA Infineon Technologies, SAF-XC878-13FFI 5V AA Datasheet - Page 96
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SAF-XC878-13FFI 5V AA
Manufacturer Part Number
SAF-XC878-13FFI 5V AA
Description
IC MCU 8BIT FLASH 64-LQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Specifications of SAF-XC878-13FFI 5V AA
Core Processor
XC800
Core Size
8-Bit
Speed
27MHz
Connectivity
SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
52KB (52K x 8)
Program Memory Type
FLASH
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000447274
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fractional divider) for generating a wide range of baud rates based on its input clock
see
Figure 26
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (
output of the prescaler (
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See
The baud rate (
•
•
•
•
Data Sheet
Input clock
Prescaling factor (2
Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional
divider mode)
8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
f
PCLK
Figure
Prescaler
26.
FDEN
FDM
Baud-rate Generator Circuitry
f
f
PCLK
f
BR
DIV
) value is dependent on the following parameters:
f
MOD
clk
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
BRPRE
f
DIV
Fractional Divider
) if the fractional divider is disabled (FDEN = 0). For baud rate
Adder
) defined by bit field BRPRE in register BCON
FDRES
1
1
FDSTEP
0
f
MOD
‘0’
f
DIV
89
0
(overflow)
FDEN&FDM
10
11
01
00
10
00
01
11
R
0
1
Section
NDOV
Functional Description
8-Bit Baud Rate Timer
8-Bit Reload Value
3.14.
XC87xCLM
V1.5, 2011-03
f
BR
f
PCLK
,
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