SAF-XC878-13FFI 5V AA Infineon Technologies, SAF-XC878-13FFI 5V AA Datasheet - Page 98

• Manufacturer Part Number: SAF-XC878-13FFI 5V AA
• Description: IC MCU 8BIT FLASH 64-LQFP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAF-XC878-13FFI 5V AA

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 27MHz
• Connectivity: SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 52KB (52K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000447274

Table 32
24 MHz
12 MHz
8 MHz
6 MHz
3.13.2
In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the
variable baud rates. In theory, this timer could be used in any of its modes. But in
practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set
to the appropriate value for the required baud rate. The baud rate is determined by the
Timer 1 overflow rate and the value of SMOD as follows:
3.14
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock f
The output frequency in normal divider mode is derived as follows:
Data Sheet
f
PCLK
Baud Rate Generation using Timer 1
Normal Divider Mode (8-bit Auto-reload Timer)
Deviation Error for UART with Fractional Divider enabled
Prescaling Factor
(2BRPRE)
1
1
1
1
MOD
that is 1/n of the input clock f
Mode 1, 3 baud rate
f
MOD
Reload Value
(BR_VALUE + 1)
6 (6
3 (3
2 (2
6 (6
=
H
H
H
H
f
)
)
)
)
DIV
91
=
---------------------------------------------------- -
32 2
×
----------------------------- -
256 STEP
2
×
SMOD
DIV
–
×
, where n is defined by 256 - STEP.
1
(
256 TH1
×
STEP
59 (3B
59 (3B
59 (3B
236 (EC
f
PCLK
–
H
H
H
Functional Description
)
)
)
H
)
)
Figure
Deviation
Error
+0.03 %
+0.03 %
+0.03 %
+0.03 %
26). Once the
XC87xCLM
V1.5, 2011-03
(3.6)
(3.7)