UPD78F1142AGA-HAB-AX Renesas Electronics America, UPD78F1142AGA-HAB-AX Datasheet - Page 178
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UPD78F1142AGA-HAB-AX
Manufacturer Part Number
UPD78F1142AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
176
(B) → (E)
(C) → (F)
(D) → (G)
Status Transition
(D) → (C)
(X1 clock: 2 MHz ≤ f
(D) → (C)
(X1 clock: 10 MHz < f
(D) → (C)
(external main clock)
(B) → (H)
(C) → (I)
Notes 1. Set the oscillation stabilization time as follows.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set
Remark (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-15.
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence of SFR registers)
2. FSEL = 1 when f
Setting Flag of SFR Register
(see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and CHAPTER 28
ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
If a divided clock is selected and f
Status Transition
Status Transition
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
X
X
≤ 10 MHz)
≤ 20 MHz)
(Setting sequence)
In X1 oscillation
External clock
CLK
> 10 MHz
CHAPTER 5 CLOCK GENERATOR
Register
Note 1
Note 1
Note 1
OSTS
User’s Manual U17854EJ9V0UD
Executing HALT instruction
Stopping peripheral
functions that cannot
operate in STOP mode
CLK
Unnecessary if the CPU is operating
with the high-speed system clock
≤ 10 MHz, use with FSEL = 0 is possible even if f
MSTOP
Register
CSC
0
0
0
Register
OSMC
FSEL
1
0/1
Note 2
0
Sets the OSTS
register
Setting
Setting
Must not be
Register
checked
checked
checked
Must be
Must be
OSTC
−
−
Unnecessary if these registers
are already set
MCM0
Executing STOP
instruction
1
1
1
Register
CKC
X
> 10 MHz.
CSS
0
0
0
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