UPD78F1142AGA-HAB-AX Renesas Electronics America, UPD78F1142AGA-HAB-AX Datasheet - Page 593
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UPD78F1142AGA-HAB-AX
Manufacturer Part Number
UPD78F1142AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
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Company:
Part Number:
UPD78F1142AGA-HAB-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.4 Interrupt Servicing Operations
15.4.1 Maskable interrupt acknowledgment
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1).
acknowledged during servicing of a higher priority interrupt request.
in Table 15-4 below.
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the
loaded into the PC and branched.
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed
For the interrupt request acknowledgment timing, see Figures 15-8 and 15-9.
Note If an interrupt request is generated just before the RET instruction, the wait time becomes longer.
Remark 1 clock: 1/f
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 15-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
Restoring from an interrupt is possible by using the RETI instruction.
Table 15-4. Time from Generation of Maskable Interrupt Until Servicing
Servicing time
CLK
(f
CLK
: CPU clock)
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U17854EJ9V0UD
9 clocks
Minimum Time
However, a low-priority interrupt request is not
14 clocks
Maximum Time
Note
591
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