UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 408
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
TMRmn
Symbol
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
MAS
Only the even channel can be set as a master channel (MASTERmn = 1).
Be sure to use odd-numbered channels as slave channels (MASTERmn = 0).
Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function.
If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1
to CISmn0 bits to 10B.
TER
CKS
STS
mn2
mn1
CIS
mn
mn
Other than above
15
0
1
0
0
0
1
0
0
1
1
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.
Operates as master channel in simultaneous channel operation function.
STS
mn1
mn0
CIS
14
0
0
1
0
0
1
0
1
0
Falling edge
Rising edge
Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
STS
mn0
Figure 8-11. Format of Timer Mode Register mn (TMRmn) (2/3)
13
0
1
0
0
0
Only software trigger start is valid (other trigger sources are unselected).
Valid edge of the TImn pin input is used as both the start trigger and capture trigger.
Both the edges of the TImn pin input are used as a start trigger and a capture trigger.
Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the simultaneous channel operation function).
Setting prohibited
CCS
mn
12
MAST
ERmn
11
simultaneously with another channel(as a slave or master)
Selection between using channel n independently or
STS
mn2
10
Setting of start trigger or capture trigger of channel n
STS
mn1
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
9
Selection of TImn pin input valid edge
STS
mn0
8
After reset: 0000H
mn1
CIS
7
mn0
CIS
6
CHAPTER 8 TIMER ARRAY UNIT
5
0
R/W
4
0
mn3
MD
3
mn2
MD
2
mn1
MD
1
mn0
MD
0
408
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