UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 497
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 497 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: FFF9EH
(3) Real-time counter control register 1 (RTCC1)
RTCC1
Symbol
The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the
counter.
The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit
after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG
and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of real-time counter
control register 1 (RTCC1), the alarm minute register (ALARMWM), the alarm hour register (ALARMWH), and the
alarm week register (ALARMWW)), set match operation to be invalid (“0”) for the WALE bit.
This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to
“1” one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when “0” is written to it.
Writing “1” to it is invalid.
WALIE
WAFG
WALE
WALE
<7>
0
1
0
1
0
1
After reset: 00H
Figure 9-4. Format of Real-Time Counter Control Register 1 (RTCC1) (1/2)
Match operation is invalid.
Match operation is valid.
Does not generate interrupt on matching of alarm.
Generates interrupt on matching of alarm.
Alarm mismatch
Detection of matching of alarm
WALIE
<6>
R/W
5
0
Control of alarm interrupt (INTRTC) function operation
WAFG
<4>
Alarm detection status flag
Alarm operation control
RIFG
<3>
CHAPTER 9 REAL-TIME COUNTER
2
0
RWST
<1>
RWAIT
<0>
497
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