UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 559
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 559 of 1171
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78K0R/Kx3-L
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
Remark f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
FR2
A/D Converter Mode Register (ADM)
×
0
0
0
0
1
1
1
1
×
×
FR1
×
0
0
1
1
0
0
1
1
×
×
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
Other than above
CLK
Sampling
: CPU/peripheral hardware clock frequency
once (ADCS = 0) beforehand.
clock frequency errors into consideration.
INTAD
ADCS
timing
FR0
×
0
1
0
1
0
1
0
1
×
×
ADCS
LV1
0
0
1
1
Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
←
LV0
clear
SAR
1 or ADS rewrite
0
1
0
1
Table 13-2. A/D Conversion Time Selection (3/3)
Setting prohibited
speed 1
speed 2
Normal
voltage
Mode
Low-
High
High
Sampling
(3) 1.8 V ≤ AV
Setting prohibited
Setting
prohibited
49.0
37.0
25.0
Setting
prohibited
Setting prohibited
Setting prohibited
Conversion time
f
CLK
= 2 MHz
Successive conversion
μ
μ
μ
s
s
s
REF
Setting
prohibited
48.4
38.8
29.2
Setting
prohibited
f
Conversion Time Selection
CLK
≤ 4.0 V
= 5 MHz
μ
μ
μ
s
s
s
generation
to ADCR,
Transfer
INTAD
48.2
24.2
Setting
prohibited
f
CLK
= 10 MHz
μ
μ
SAR
clear
s
s
CHAPTER 13 A/D CONVERTER
Conversion time
Sampling
24.1
Setting
prohibited
f
CLK
= 20 MHz
μ
s
f
f
f
f
f
f
f
f
Conversion
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Clock (f
/20
/10
/8
/6
/4
/3
/2
−
−
AD
)
559
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