UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 782
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
15.5.6 Wait
data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE = 1)
Transfer lines
Master
Slave
ACKE
SDA0
SCL0
SCL0
SCL0
IICA
IICA
H
D2
6
6
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
D1
7
7
Figure 15-20. Wait (1/2)
D0
8
8
Wait from slave
9
ACK
Wait after output
of ninth clock
9
FFH is written to IICA or WREL is set to 1
CHAPTER 15 SERIAL INTERFACE IICA
Wait from master
IICA data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
782
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