UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 599
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 599 of 1171
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03),
Note
Caution Be sure to clear bits 3, 6, and 11 to “0”. Be sure to set bit 2 to “1”.
SCRmn
Symbol
(Remark is listed on the next page.)
Figure 14-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/4)
F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13),
F020CH, F020DH (SCR20), F020EH, F020FH (SCR21)
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I
EOC
Set EOCmn = 0 in the CSI mode, simplified I
Set EOCmn = 1 during UART reception.
DAP
TXE
mn
mn
mn
When using CSI01 not with EOC01 = 0, error interrupt INTSRE0 may be generated.
0
0
1
1
0
0
1
1
0
1
TXE
mn
15
Masks error interrupt INTSREx (INTSRx is not masked).
Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
RXE
CKP
mn
mn
0
1
0
1
0
1
0
1
RXE
mn
14
Disable communication.
Reception only
Transmission only
Transmission/reception
DAP
mn
13
CKP
Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
mn
12
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
SCKp
SOp
SIp input timing
Selection of data and clock phase in CSI mode
11
0
EOC
mn
10
2
C mode, and during UART transmission
D7 D6 D5 D4 D3 D2 D1 D0
Setting of operation mode of channel n
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PTC
mn1
9
PTC
mn0
8
After reset: 0087H
DIR
mn
7
2
CHAPTER 14 SERIAL ARRAY UNIT
C mode.
6
0
SLC
mn1
5
R/W
Note
SLC
mn0
.
4
3
0
DLS
mn2
2
Type
1
2
3
4
DLS
mn1
1
DLS
mn0
0
599
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