SAK-XC2287-96F80L AC Infineon Technologies, SAK-XC2287-96F80L AC Datasheet - Page 43

• Manufacturer Part Number: SAK-XC2287-96F80L AC
• Description: IC MCU 16BIT 768KB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: XC22xxr

Specifications of SAK-XC2287-96F80L AC

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: DMA, I²S, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2
All external memory access operations are performed by a special on-chip External Bus
Controller (EBC). The EBC also controls access to resources connected to the on-chip
LXBus (MultiCAN and the USIC modules). The LXBus is an internal representation of
the external bus that allows access to integrated peripherals and modules in the same
way as to external components.
The EBC can be programmed either to Single Chip Mode, when no external memory is
required, or to an external bus mode with the following selections
•
•
•
The bus interface uses Port 10 and Port 2 for addresses and data. In the demultiplexed
bus modes, the lower addresses are output separately on Port 0 and Port 1. The number
of active segment address lines is selectable, restricting the external address space to
8 Mbytes … 64 Kbytes. This is required when interface lines shall be assigned to Port 2.
Up to five external CS signals (four windows plus default) can be generated and output
on Port 4 in order to save external glue logic. External modules can be directly
connected to the common address/data bus and their individual select lines.
A HOLD/HLDA protocol is available for bus arbitration; this allows the sharing of external
resources with other bus masters. The bus arbitration is enabled by software, after which
pins P3.0 … P3.2 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In
Master Mode (default after reset) the HLDA pin is an output. In Slave Mode pin HLDA is
switched to be an input. This allows the direct connection of the slave controller to
another master controller without glue logic.
Important timing characteristics of the external bus interface are programmable (with
registers TCONCSx/FCONCSx) to allow the user to adapt it to a wide range of different
types of memories and external peripherals.
Access to very slow memories or modules with varying access times is supported by a
special ‘Ready’ function. The active level of the control input signal is selectable.
In addition, up to four independent address windows may be defined (using registers
ADDRSELx) to control access to resources with different bus characteristics. These
address windows are arranged hierarchically where window 4 overrides window 3, and
window 2 overrides window 1. All accesses to locations not covered by these four
address windows are controlled by TCONCS0/FCONCS0. The currently active window
can generate a chip select signal.
The external bus timing is based on the rising edge of the reference clock output
CLKOUT. The external bus protocol is compatible with that of the standard C166 Family.
1) Bus modes are switched dynamically if several address windows with different mode settings are used.
Data Sheet
Address Bus Width with a range of 0 … 24-bit
Data Bus Width 8-bit or 16-bit
Bus Operation Multiplexed or Demultiplexed
External Bus Controller
41
XC2000 Family Derivatives
XC2287 / XC2286 / XC2285
Functional Description
1)
:
V2.1, 2008-08