AT90LS4433-4AC Atmel, AT90LS4433-4AC Datasheet - Page 51

• Manufacturer Part Number: AT90LS4433-4AC
• Description: IC MCU 4K 4MHZ A/D LV 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS4433-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SPI Control Register – SPCR
1042H–AVR–04/03
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the global interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 38 and Figure 39 for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 38 or Figure 39 for the functionality of this bit.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
clock frequency (f
Table 18. Relationship between SCK and the Oscillator Frequency
Bit
$0D ($2D)
Read/Write
Initial Value
SPR1
0
0
1
1
SPIE
R/W
7
0
cl
) is shown in Table 18.
SPE
R/W
6
0
SPR0
DORD
0
1
0
1
R/W
5
0
MSTR
R/W
4
0
CPOL
R/W
3
0
CPHA
R/W
2
0
SCK Frequency
AT90S/LS4433
f
f
f
cl
f
cl
cl
/128
SPR1
cl
/16
/64
R/W
/4
1
0
SPR0
R/W
0
0
SPCR
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