AT90LS4433-4AC Atmel, AT90LS4433-4AC Datasheet - Page 69

• Manufacturer Part Number: AT90LS4433-4AC
• Description: IC MCU 4K 4MHZ A/D LV 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS4433-4AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADC Data Register – ADCL
AND ADCH
1042H–AVR–04/03
• Bit 5 – ADFR: ADC Free Run Select
When this bit is set (one), the ADC operates in Free Run mode. In this mode, the ADC
samples and updates the Data Registers continuously. Clearing this bit (zero) will termi-
nate Free Run mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the Data Registers are
updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-
bit in SREG are set (one). ADIF is cleared by hardware when executing the correspond-
ing interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the
flag. Beware that if doing a Read-Modify-Write on ADCSR, a pending interrupt can be
disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete interrupt is activated.
• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 22. ADC Prescaler Selections
When an ADC conversion is complete, the result is found in these two registers. In Free
Run mode, it is essential that both registers are read and that ADCL is read before
ADCH.
Bit
$05 ($25)
$04 ($26)
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC7
15
R
R
–
7
0
0
ADC6
14
ADPS1
R
R
–
6
0
0
0
0
1
1
0
0
1
1
ADC5
13
R
R
–
5
0
0
ADC4
12
R
R
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
11
R
R
–
3
0
0
ADC2
10
R
R
–
2
0
0
AT90S/LS4433
ADC9
ADC1
Division Factor
R
R
9
1
0
0
128
16
32
64
2
2
4
8
ADC8
ADC0
8
0
R
R
0
0
ADCH
ADCL
69