ATMEGA8535-16MI Atmel, ATMEGA8535-16MI Datasheet - Page 104
![IC AVR MCU 8K 16MHZ IND 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA8535-16MI
Manufacturer Part Number
ATMEGA8535-16MI
Description
IC AVR MCU 8K 16MHZ IND 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Phase Correct PWM Mode
104
ATmega8535(L)
The counter will then have to count to the MAX value (0xFFFF) and wrap around start-
ing at 0x0000 before the Compare Match can occur. The OCR1A Register however, is
double buffered. This feature allows the OCR1A I/O location to be written anytime.
When the OCR1A I/O location is written the value written will be put into the OCR1A
Buffer Register. The OCR1A Compare Register will then be updated with the value in
the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is
done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By
using ICR1, the OCR1A Register is free to be used for generating a PWM output on
OC1A. However, if the base PWM frequency is actively changed (by changing the TOP
value), using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 46
on page 111). The actual OC1x value will only be visible on the port pin if the data direc-
tion for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
setting (or clearing) the OC1x Register at the Compare Match between OCR1x and
TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter
is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The “N” variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating
a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM
(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the
OCR1x equal to TOP will result in a constant high or low output (depending on the polar-
ity of the output set by the COM1x1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1).
This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The wave-
form generated will have a maximum frequency of f
zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou-
ble buffer feature of the output compare unit is enabled in the fast PWM mode.
T h e p h a s e c o r r e c t P u l s e W i d t h M o d u la t i o n o r p h a s e c o r r e c t P W M m o d e
(WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform
generation option. The phase correct PWM mode is, like the phase and frequency cor-
rect PWM mode, based on a dual-slope operation. The counter counts repeatedly from
BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare
Output mode, the Output Compare (OC1x) is cleared on the Compare Match between
TCNT1 and OCR1x while up-counting and set on the Compare Match while down-
counting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. How-
ever, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or
f
OCnxPWM
=
---------------------------------- -
N
⋅
(
f
clk_I/O
1
+
OC
TOP
1
A
= f
)
clk_I/O
/2 when OCR1A is set to
2502K–AVR–10/06
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