ATMEGA8535-16MI Atmel, ATMEGA8535-16MI Datasheet - Page 232
![IC AVR MCU 8K 16MHZ IND 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA8535-16MI
Manufacturer Part Number
ATMEGA8535-16MI
Description
IC AVR MCU 8K 16MHZ IND 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Setting the Boot Loader Lock
Bits by SPM
EEPROM Write Prevents
Writing to SPMCR
Reading the Fuse and Lock
Bits from Software
232
ATmega8535(L)
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to
SPMCR and execute SPM within four clock cycles after writing SPMCR. The only
accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot
Loader section from any software update by the MCU.
See Table 89 and Table 90 for how the different settings of the Boot Loader bits affect
the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCR. The Z-pointer is don’t care during this operation, but for future compatibility it is
recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock
bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to “1”
when writing the Lock bits. When programming the Lock bits the entire Flash can be
read during the operation.
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEWE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCR
Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When
an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN
bits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-
ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock
bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is
executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for
reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set
the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within
three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the
Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to
Table 99 on page 239 for a detailed description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination reg-
ister as shown below. Refer to Table 98 on page 238 for detailed description and
mapping of the Fuse High bits.
Bit
R0
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
1
7
–
7
7
FLB6
FHB6
6
1
6
–
6
6
BLB12
BLB12
FHB5
FLB5
5
5
5
5
BLB11
BLB11
FHB4
FLB4
4
4
4
4
BLB02
BLB02
FHB3
FLB3
3
3
3
3
BLB01
BLB01
FHB2
FLB2
2
2
2
2
FHB1
FLB1
LB2
1
1
1
1
1
FLB0
FHB0
LB1
2502K–AVR–10/06
0
1
0
0
0
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