AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 102
AT89C5131-S3SIL
Manufacturer Part Number
AT89C5131-S3SIL
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5131-S3SIL.pdf
(176 pages)
Specifications of AT89C5131-S3SIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Slave Receiver Mode
Slave Transmitter Mode
102
AT89C5131
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table . After a repeated START condition (state 10h) SSLC may switch to the master
transmitter mode by loading SSDAT with SLA+W.
In the slave receiver mode, a number of data bytes are received from a master transmit-
ter (Figure 51). To initiate the slave receiver mode, SSADR and SSCON must be loaded
as follows:
Table 78. SSADR: Slave Receiver Mode Initialization
The upper 7 bits are the address to which SSLC will respond when addressed by a mas-
ter. If the LSB (GC) is set SSLC will respond to the general call address (00h); otherwise
it ignores the general call address.
Table 79. SSCON: Slave Receiver Mode Initialization
CR0, CR1 and CR2 have no effect in the slave mode (Table 82). SSIE must be set to
enable SSLC. The AA bit must be set to enable the own slave address or the general
call address acknowledgement. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, SSLC waits until it is addressed by its
own slave address followed by the data direction bit which must be at logic 0 (W) for
SSLC to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine.The appro-
priate action to be taken for each of these status code is detailed in Table 84. The slave
receiver mode may also be entered if arbitration is lost while SSLC is in the master
mode (states 68h and 78h of Table 84).
If the AA bit is reset during a transfer, SSLC will return a not acknowledge (logic 1) to
SDA after the next received data byte. While AA is reset, SSLC does not respond to its
own slave address. However, the TWI bus is still monitored and address recognition
may be resume at any time by setting AA. This means that the AA bit may be used to
temporarily isolate SSLC from the TWI bus.
In the slave transmitter mode, a number of data bytes are transmitted to a master
receiver (Figure 52). Data transfer is initialized as in the slave receiver mode. When
SSADR and SSCON have been initialized, SSLC waits until it is addressed by its own
slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to
operate in the slave transmitter mode. After its own slave address and the R bit have
been received, the serial interrupt flag is set and a valid status code can be read from
SSCS. This status code is used to vector to an interrupt service routine. The appropriate
action to be taken for each of these status code is detailed in Table 83. The slave trans-
mitter mode may also be entered if arbitration is lost while SSLC is in the master mode
(state B0h of Table 83).
bit rate
CR2
A6
SSIE
A5
1
STA
A4
0
own slave address
STO
A3
0
A2
SI
0
AA
A1
1
bit rate
CR1
A0
4136B–USB–09/03
bit rate
CR0
GC
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