AT89C5131-S3SIL Atmel, AT89C5131-S3SIL Datasheet - Page 150
AT89C5131-S3SIL
Manufacturer Part Number
AT89C5131-S3SIL
Description
IC 8051 MCU FLASH 32K USB 52PLCC
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5131-S3SIL.pdf
(176 pages)
Specifications of AT89C5131-S3SIL
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
For Use With
AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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WDT During Power-down
and Idle
150
AT89C5131
Table 108. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C5131 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C5131 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic
Bit
S2
S1
S0
-
-
-
-
-
6
-
Description
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
5
-
0
1
0
1
0
1
0
1
(214 - 1) machine cycles, 16.3 ms at FOSCA = 12 MHz
(215 - 1) machine cycles, 32.7 ms at FOSCA = 12 MHz
(216 - 1) machine cycles, 65.5 ms at FOSCA = 12 MHz
(217 - 1) machine cycles, 131 ms at FOSCA = 12 MHz
(218 - 1) machine cycles, 262 ms at FOSCA = 12 MHz
(219 - 1) machine cycles, 542 ms at FOSCA = 12 MHz
(220 - 1) machine cycles, 1.05 s at FOSCA = 12 MHz
(221 - 1) machine cycles, 2.09 s at FOSCA = 12 MHz
4
-
3
-
S2
2
S1
1
4136B–USB–09/03
S0
0
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