AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 321

• Manufacturer Part Number: AT91SAM7S32-AU-001
• Description: IC ARM7 MCU 32BIT 32K 48LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32-AU-001

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S32-AU001

Figure 30-10. Master Read with Multiple Data Bytes
30.7.6
30.7.6.1
6175K–ATARM–30-Aug-10
TXCOMP
RXRDY
TWD
Internal Address
S
7-bit Slave Addressing
Write START Bit
DADR
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 30-9. Master Read with One Data Byte
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 30-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
R
A
and
TXCOMP
DATA n
RXRDY
Figure 30-13
TWD
Figure
Read RHR
A
S
DATA n
Write START &
30-10. For Internal Address usage see
for Master Write operation with internal address.
DATA (n+1)
STOP Bit
DADR
AT91SAM7S Series Preliminary
A
DATA (n+1)
Read RHR
R
DATA (n+m)-1
Figure
A
30-9. When a multiple data byte read is
DATA
DATA (n+m)-1
A
Read RHR
after next-to-last data read
DATA (n+m)
Read RHR
Write STOP Bit
Section
N
P
Figure
30.7.6.
N
30-12. See
DATA (n+m)
Read RHR
P
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