AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 409
![IC ARM7 MCU 32BIT 32K 48LQFP](/photos/6/76/67647/453-48-lqfp_sml.jpg)
AT91SAM7S32-AU-001
Manufacturer Part Number
AT91SAM7S32-AU-001
Description
IC ARM7 MCU 32BIT 32K 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S32-AU-001
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S32-AU001
Available stocks
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Part Number
Manufacturer
Quantity
Price
- Current page: 409 of 779
- Download datasheet (11Mb)
32.6.1.1
32.6.1.2
6175K–ATARM–30-Aug-10
Clock Divider
Transmitter Clock Management
Figure 32-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its
maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division
by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this
field is programmed to 0, the Clock Divider is not used and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Mas-
ter Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master
Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of
whether the DIV value is even or odd.
Figure 32-5.
Table 32-2.
The transmitter clock is generated from the receiver clock or the divider clock or an external
clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in
SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by
the CKI bits in SSC_TCMR.
Maximum
MCK / 2
Divided Clock Generation
Divided Clock
Divided Clock
Master Clock
Master Clock
DIV = 3
DIV = 1
MCK
AT91SAM7S Series Preliminary
/ 2
Divided Clock Frequency = MCK/2
Divided Clock Frequency = MCK/6
Clock Divider
12-bit Counter
MCK / 8190
Minimum
SSC_CMR
Divided Clock
409
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