AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 504
![IC ARM7 MCU 32BIT 32K 48LQFP](/photos/6/76/67647/453-48-lqfp_sml.jpg)
AT91SAM7S32-AU-001
Manufacturer Part Number
AT91SAM7S32-AU-001
Description
IC ARM7 MCU 32BIT 32K 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S32-AU-001
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S32-AU001
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35.5.2
35.5.2.1
504
AT91SAM7S Series Preliminary
Handling Transactions with USB V2.0 Device Peripheral
Setup Transaction
Figure 35-4. Control Read and Write Sequences
Notes:
Setup is a special type of host-to-device transaction used during control transfers. Control trans-
fers must be performed using endpoints with no ping-pong attributes. A setup transaction needs
to be handled as soon as possible by the firmware. It is used to transmit requests from the host
to the device. These requests are then handled by the USB device and may require more argu-
ments. The arguments are sent to the device by a Data OUT transaction which follows the setup
transaction. These requests may also return data. The data is carried out to the host by the next
Data IN transaction which follows the setup transaction. A status transaction ends the control
transfer.
When a setup transfer is received by the USB endpoint:
Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read
the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the
setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data
OUT transfer and overwrite the setup packet in the FIFO.
• The USB device automatically acknowledges the setup packet
• RXSETUP is set in the UDP_ CSRx register
• An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is
carried out to the microcontroller if interrupts are enabled for this endpoint.
Control Read
Control Write
No Data
Control
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT
data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specifi-
cation, Rev. 2.0, for more information on the protocol layer.
transaction with no data).
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
Status Stage
Status IN TX
Data OUT TX
Data IN TX
Data Stage
Data Stage
Data OUT TX
Data IN TX
6175K–ATARM–30-Aug-10
Status OUT TX
Status Stage
Status IN TX
Status Stage
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