AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 648
AT91SAM7S32-AU-001
Manufacturer Part Number
AT91SAM7S32-AU-001
Description
IC ARM7 MCU 32BIT 32K 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S32-AU-001
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S32-AU001
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40.10.2.11
40.10.3
40.10.3.1
40.10.4
40.10.4.1
648
AT91SAM7S Series Preliminary
Master Clock (MCK)
Non Volatile Memory Bits (NVM Bits)
ADC: Sleep Mode
MCK: Limited Master Clock Frequency Ranges
NVM Bits: Write/Erase Cycles Number
Problem Fix/Workaround
None.
If Sleep mode is activated while there is no activity (no conversion is being performed), it will
take effect only after a conversion occurs.
To activate sleep mode as soon as possible, it is recommended to write successively, ADC
Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digi-
tal conversion, in order put ADC into sleep mode at the end of this conversion.
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be
lower than 3 MHz or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed
and either data or prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State)
as stated in
Note:
The user must ensure that the device is running at the authorized frequency by programming the
PLL properly to not run within the forbidden frequency range.
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 128 KB Flash memory, it
remains at 10K for the Flash memory.
None.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency
with only 1 wait state.
Table 37-24, “Embedded Flash Wait States,” on page
578, are still applicable.
6175K–ATARM–30-Aug-10
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