ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 139

• Manufacturer Part Number: ATMEGA165-16MI
• Description: IC AVR MCU 16K 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165-16MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Peripheral
Interface – SPI
2573G–AVR–07/09
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega165 and peripheral devices or between several AVR devices. The
ATmega165 SPI includes the following features:
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The PRSPI bit in “Power Reduction Register - PRR” on page 34 must be written to zero
to enable SPI module.
Figure 65. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.
The system consists of two shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
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1. Refer to Figure 1 on page 2, and Table 27 on page 62 for SPI pin placement.
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