ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 87
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ATMEGA165-16MI
Manufacturer Part Number
ATMEGA165-16MI
Description
IC AVR MCU 16K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Timer/Counter Register –
TCNT0
2573G–AVR–07/09
Table 45 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to
phase correct PWM mode.
Table 45. Compare Output Mode, Phase Correct PWM Mode
Note:
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 46. Clock Select Bit Description
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the compare match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a compare match between TCNT0
and the OCR0A Register.
Bit
Read/Write
Initial Value
CS02
COM0A1
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
CS01
the compare match is ignored, but the set or clear is done at TOP. See “Phase Cor-
rect PWM Mode” on page 82 for more details.
0
0
1
1
0
0
1
1
R/W
COM0A0
7
0
CS00
0
1
0
1
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge.
External clock source on T0 pin. Clock on rising edge.
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when downcounting.
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when downcounting.
I/O
I/O
I/O
I/O
I/O
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
5
0
R/W
4
0
TCNT0[7:0]
R/W
3
0
R/W
2
0
ATmega165/V
(1)
R/W
1
0
R/W
0
0
TCNT0
87
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