ATMEGA165-16MI Atmel, ATMEGA165-16MI Datasheet - Page 152
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ATMEGA165-16MI
Manufacturer Part Number
ATMEGA165-16MI
Description
IC AVR MCU 16K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock
Frame Formats
2573G–AVR–07/09
input (Slave) or clock output (Master). The dependency between the clock edges and
data sampling or data change is the same. The basic principle is that data input (on
RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is
changed.
Figure 71. Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and
which is used for data change. As Figure 71 shows, when UCPOL is zero the data will
be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the
data will be changed at falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start
and stop bits), and optionally a parity bit for error checking. The USART accepts all 30
combinations of the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-
plete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 72 illustrates the possible
combinations of the frame formats. Bits inside brackets are optional.
Figure 72. Frame Formats
St
(n)
P
UCPOL = 1
UCPOL = 0
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
(IDLE)
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
RxD / TxD
RxD / TxD
St
XCK
XCK
0
1
2
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
ATmega165/V
Sp1 [Sp2]
(St / IDLE)
152
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