ATMEGA88V-10AU Atmel, ATMEGA88V-10AU Datasheet - Page 136
![IC AVR MCU 8K 10MHZ 1.8V 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA88V-10AU
Manufacturer Part Number
ATMEGA88V-10AU
Description
IC AVR MCU 8K 10MHZ 1.8V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA88V-10AU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
2-Wire, SPI, USART, Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3 bit
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA88V-10AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATMEGA88V-10AUR
Manufacturer:
Atmel
Quantity:
1 991
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16. Timer/Counter0 and Timer/Counter1 Prescalers
16.0.1
16.0.2
16.0.3
136
ATmega48/88/168
Internal Clock Source
Prescaler Reset
External Clock Source
“8-bit Timer/Counter0 with PWM” on page 88
107
tings. The description below applies to both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, that is, operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
logic. The synchronized (sampled) signal is then passed through the edge detector.
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (
is transparent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 16-1. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
CLK_I/O
T1
share the same prescaler module, but the Timer/Counters can have different prescaler set-
/clk
/1024.
Tn
clk
T0
I/O
). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
CLK_I/O
D
LE
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
D
Q
T1
/clk
T
0
pulse for each positive (CSn2:0 = 7) or negative
and
“16-bit Timer/Counter1 with PWM” on page
D
CLK_I/O
Q
/8, f
CLK_I/O
Edge Detector
/64, f
clk
CLK_I/O
2545S–AVR–07/10
I/O
Tn_sync
(To Clock
Select Logic)
Figure 16-1
). The latch
/256, or
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