AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 104
AT91SAM7SE256-CU
Manufacturer Part Number
AT91SAM7SE256-CU
Description
IC ARM7 MCU FLASH 256K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
Note:
19.2.3
19.2.4
104
ARM Request (16-bit)
Buffer (32 bits)
Data To ARM
Flash Access
Master Clock
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
Code Fetch
SAM7SE512/256/32 Preliminary
Write Operations
Flash Commands
@Byte 0
3 Wait State Cycles
The internal memory area reserved for the embedded Flash can also be written through a write-
only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap
around within the internal memory area address space and appear to be repeated 1024 times
within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states
for read operations + 1, except for FWS = 3 (see
The EFC offers a command set to manage programming the memory flash, locking and unlock-
ing lock sectors, consecutive programming and locking, and full Flash erasing.
Table 19-1.
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Set General-purpose NVM Bit
Clear General-purpose NVM Bit
Set Security Bit
Bytes 0-3
Set of Commands
@2
0-1
3 Wait State Cycles
@4
2-3
Bytes 0-3
Bytes 4-7
@6
4-5
3 Wait State Cycles
@8
6-7
“MC Flash Mode Register” on page
Bytes 8-11
Bytes 4-7
Value
0x0B
0x0D
0x0F
0x01
0x02
0x03
0x04
0x08
@10
8-9 10-11
3 Wait State Cycles
@12
Mnemonic
WP
SLB
WPL
CLB
EA
SGPB
CGPB
SSB
Bytes 12-15
6222F–ATARM–14-Jan-11
Bytes 8-11
111).
12-13
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