AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 143
AT91SAM7SE256-CU
Manufacturer Part Number
AT91SAM7SE256-CU
Description
IC ARM7 MCU FLASH 256K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 21-4.
21.6.5.3
6222F–ATARM–14-Jan-11
Mode
Attribute Memory
Common Memory
I/O Mode
Task File
Data Register
Control Register
Alternate Status Read
Drive Address
Standby Mode or
Address Space is not
assigned to CF
Read/Write Signals
CFCE1 and CFCE2 Truth Table
In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command
signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deac-
tivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are
driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated.
21-4 on page 144
presents the signal decoding.
Attribute memory mode, common memory mode and I/O mode are supported by setting the
address setup and hold time on the NCS4 (and/or NCS2) chip select to the appropriate values.
For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the
Static Memory Controller Section.
CFCE2
NUB
NUB
NUB
1
1
1
1
0
0
1
CFCE1
shows a schematic representation of this logic and
NLB
NLB
NLB
0
0
0
0
1
1
1
Alternate True IDE Mode
True IDE Mode
16 bits
16 bits
16 bits
16bits
DBW
8 bits
8 bits
8 bits
Don’t
8 bits
Don’t
Care
Care
SAM7SE512/256/32 Preliminary
Comment
Access to Even Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[15:8]
Access to Even Byte on D[7:0]
Access to Odd Byte on D[7:0]
Don’t Care
Table 21-5 on page 144
Don’t Care
SMC Access Mode
Byte Select
Byte Select
Don’t Care
Byte Select
Don’t Care
Don’t Care
Byte Select
Don’t Care
Don’t Care
Figure
143
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