AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 173
AT91SAM7SE256-CU
Manufacturer Part Number
AT91SAM7SE256-CU
Description
IC ARM7 MCU FLASH 256K 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, SPI, TWI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
AT91SAM7SE256-CJ
Available stocks
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Part Number
Manufacturer
Quantity
Price
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22.6.4.5
6222F–ATARM–14-Jan-11
Early Read Wait State
Figure 22-17. Chip Select Wait State
Notes:
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins (see
grammed wait states (i.e., data float wait state).
No wait state is added when a read cycle is followed by a write cycle, between consecutive
accesses of the same type, or between external and internal memory accesses.
Figure 22-18. Early Read Wait States
1. Early Read Protocol
2. Standard Read Protocol
A[22:0]
D[15:0]
NWE
MCK
A[22:0]
NCS1
NCS2
NRD
NWE
MCK
NRD
NCS
Figure
(1)
Write Cycle
addr Mem 1
22-18). This wait state is generated in addition to any other pro-
Mem 1
SAM7SE512/256/32 Preliminary
(2)
Early Read Wait
Chip Select Wait
addr Mem 2
Read Cycle
Mem 2
173
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