PXAC37KFA/00,512 NXP Semiconductors, PXAC37KFA/00,512 Datasheet - Page 47

• Manufacturer Part Number: PXAC37KFA/00,512
• Description: IC XA MCU 16BIT 32K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: XAr

Specifications of PXAC37KFA/00,512

• Core Processor: XA
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-3533-5; 935266516512; PXAC37KFA

1. For a Standard CAN Frame Message Object, only 27 bits plus IDE (11 bits of CAN ID + 2x8 bits + IDE ) from the incoming message are
1. Note: For transmit objects, the frame information is programmed in this register.
Philips Semiconductors
OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL)
OBJECT N MASK FIELD (MNMSKH AND MNMSKL)
SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM)
NOTE:
In many applications based on Standard CAN frames, either Data
Byte 1, Data Byte 2, or both do not participate in Acceptance
Filtering. Therefore, the User is required to Mask out the unused
Data Byte(s).
OBJECT N MATCH ID FIELD (MNMIDH AND MNMIDL)
OBJECT N MASK FIELD (MNMSKH AND MNMSKL)
SCREENER ID FIELD (ASSEMBLED FROM INCOMING BIT–STREAM)
MnMIDH: Message n Match ID High Word
MNMIDH
MnMIDL: Message n Match ID Low Word
MNMIDL
MnMSKH: Message n Mask High Word
MNMSKH
NOTE:
MnMSKL: Message n Mask Low Word
2000 Jan 25
Mid28 – Mid18
Msk28 – Msk18
CAN ID.28 – CAN ID.18
Mid28 – Mid18
Msk28 – Msk18
CAN ID.28 – CAN ID.0
Mid28
Msk28
Mid12
Address: MMR base + n0h
Address: MMR base + n2h
Access: Read, write. Word access only.
Address: MMR base + n4h
Address: MMR base + n6h
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
15
15
routed to the acceptance filter. The User is therefore required to set the Msk1 and Msk0 bits in the Mask field for that object (i.e., “don’t
care”). The IDE bit is not Maskable.
15
Mid27
Msk27
14
14
Mid11
14
Mid26
Msk26
13
13
Mid10
13
Mid25
Msk25
12
12
Mid9
12
Mid24
Msk24
11
11
Mid8
11
Mid17 – Mid10
Data Byte 1 [7:0]
Mid17 – Mid10
Mid23
Msk23
10
10
Msk17 – Msk10
Msk17 – Msk10
Mid7
10
Mid22
Msk22
9
9
Mid6
9
Mid21
Msk21
8
8
Mid5
8
40
Mid20
Msk20
Screener ID Field for Extended CAN Frame
The following table shows how the Screener ID field is assembled
from the incoming bits of an Extended CAN Frame, and how it is
compared to the Match ID and Mask fields of Object n. Note: The
IDE bit is not Maskable.
7
7
Mid4
Mid9 – Mid2
Data Byte 2 [7: 0]
Mid9 – Mid2
Access: Read, write. Word access only.
Reset value: xxxxh
Reset value: xxxxxxxxxxxxxx00b (unused bits are always read as
‘0’)
Access: Read, write. Word access only.
Reset value: xxxxh
Access: Read, write. Word access only.
Reset value: xxxxxxxxxxxxx000b (unused bits are always read as
‘0’)
7
Mid19
Msk19
Msk9 – Msk2
Msk9 – Msk2
6
6
Mid3
6
Mid18
Msk18
5
Mid2
5
5
Mid17
Msk17
Mid1
4
4
4
Mid16
Msk16
Mid0
3
3
3
Mid1
Mid1
x
Mid15
Msk15
MIDE
Preliminary specification
2
2
2
Msk1
Msk1
Mid0
Mid0
x
Mid14
Msk14
XA-C3
1
1
1
–
Msk0
Msk0
MIDE
MIDE
IDE
IDE
Mid13
Msk13
0
0
0
–