LH79524N0F100A1,55 NXP Semiconductors, LH79524N0F100A1,55 Datasheet - Page 6

• Manufacturer Part Number: LH79524N0F100A1,55
• Description: IC ARM7 BLUESTREAK MCU 208LFBGA
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79524N0F100A1,55

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 76.2MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LFBGA
• For Use With: SDK-LH79524-10-3216R - KIT DEVELOPMENT ZOOM SDK LH79524460-3474 - KIT DEV ZOOM STARTER FOR LH79524568-4305 - BOARD EVAL FOR LH79524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 568-4272; 935285053551; LH79524N0F100A1-S

LH79524/LH79525
6
LFBGA
K14
A16
A15
PIN
J16
M2
M1
M4
G2
H2
H3
G3
G1
N1
R2
R1
N3
N2
E2
F2
F1
F3
E1
L3
L2
L1
K3
K2
P2
P1
J3
nOE
nWE
USBDN
USBDP
AN0/UL/X+
AN1/UR/X–
AN2/LL/Y+/PJ3
AN3/LR/Y–/PJ0
AN4/WIPER/PJ1
AN5/PJ5/INT5
AN6/PJ7/INT7
AN7/PJ6/INT6
AN8/PJ4
AN9/PJ2
CTCLK/INT4/BATCNTL
PA0/INT2/UARTRX2/
UARTIRRX2
PA1/INT3/UARTTX2/
UARTIRTX2
PA2/CTCAP0A/
CTCMP0A
PA3/CTCAP0B/
CTCMP0B
PA4/CTCAP1A/
CTCMP1A
PA5/CTCAP1B/
CTCMP1B
PA6/CTCAP2A/
CTCMP2A/SDA
PA7/CTCAP2B/
CTCMP2B/SCL
PB0/nDACK/
nUARTCTS0
PB1/DREQ/
nUARTRTS0
PB2/SSPFRM/I2SWS
PB3/SSPCLK/I2SCLK
PB4/SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
PB5/SSPTX/I2STXD/
UARTTX1/UARTIRTX1
PB6/INT0/UARTRX0/
UARTIRRX0
SIGNAL NAME
TYPE
Table 2. LH79524 Pin Descriptions (Cont’d)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I
Static Memory Output Enable
Static Memory Write Enable
USB Data Negative (Differential Pair output, single ended and Differential pair input)
USB Data Positive (Differential Pair output, single ended and Differential pair input)
ADC Input 0, 4-wire touch screen Upper Left, 5-wire touch screen X+
ADC Input 1, 4-wire touch screen Upper Right, 5-wire touch screen X–
ADC Input 2, 4-wire touch screen Lower Left, 5-wire touch screen Y+; multiplexed
with GPIO Port J3 (input only)
ADC Input 3, 4-wire touch screen Upper Right, 5-wire touch screen Y–;
multiplexed with GPIO Port J0 (input only)
ADC Input 4, 5-wire touch screen Wiper input; multiplexed with GPIO Port J1
(input only)
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
ADC Input 8; multiplexed with GPIO Port J4 (input only)
ADC Input 9; multiplexed with GPIO Port J2 (input only)
Timer[2:0] External Clock input; muxed with External Int 4 and Battery Control
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0
Capture A input and Counter/Timer 0 Compare A output
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0
Capture B input and Counter/Timer 0 Compare B output
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1
Capture A input and Counter/Timer 1 Compare A output
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1
Capture B input and Counter/Timer 1 Compare B output
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2
Capture A input, Counter/Timer 2 Compare A output, I
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2
Capture B input, Counter/Timer 2 Compare B output, I
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I
UART1 Serial Data In, and UART1 Infrared Data In
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I
Out, UART1 Data Out, and UART1 IR Data Out
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
NXP Semiconductors
2
Rev. 01 — 16 July 2007
S Frame Output
DESCRIPTION
2
2
C Bus Data (open drain)
C Bus Clock (open drain)
Preliminary data sheet
System-on-Chip
2
S Data In,
2
2
S Clock
S Data