MC68HC11K1CFN4 Freescale Semiconductor, MC68HC11K1CFN4 Datasheet - Page 115
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MC68HC11K1CFN4
Manufacturer Part Number
MC68HC11K1CFN4
Description
IC MCU 640 EEPROM 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11K1CFN4
Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Type
ROMless
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
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5.4 Effects of Reset
M68HC11K Family
MOTOROLA
When the MCU recognizes a reset condition, it forces the CPU registers
and control bits to established initial states. These in turn force the
on-chip peripheral systems to known startup states, as described here.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Central processor unit (CPU)
– The stack pointer and other CPU registers are indeterminate
– The X and I interrupt mask bits are set to mask any interrupt
Memory map
– The INIT register is initialized to $00, putting the control
– The 1.5 Kbytes of RAM are at locations $0080–$067F except
– The INIT2 register is $00, locating the EEPROM at
Timer
– The timing system is initialized to a count of $0000.
– The prescaler bits are cleared, and all output compare
– All input capture registers are indeterminate after reset.
– The output compare 1 mask (OC1M) register is cleared so that
– All input capture edge-detector circuits are configured for
– The timer overflow interrupt flag and all eight timer function
immediately after reset, except for three bits in the condition
code register (CCR).
requests, and the S bit in the CCR is set to inhibit the stop
mode.
registers at locations $0000–$007F.
for the M68HC11KS Family, which has 1 Kbytes of RAM at
locations $0080–$047F.
$0D80–$0FFF.
registers are initialized to $FFFF.
successful OC1 compares do not affect any input/output (I/O)
pins. The other four output compares are configured so that
they do not affect any I/O pins on successful compares.
capture disabled operation.
interrupt flags are cleared.
Go to: www.freescale.com
Resets and Interrupts
Resets and Interrupts
Effects of Reset
Technical Data
115
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