MC68HC11K1CFN4 Freescale Semiconductor, MC68HC11K1CFN4 Datasheet - Page 62

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MC68HC11K1CFN4

Manufacturer Part Number
MC68HC11K1CFN4
Description
IC MCU 640 EEPROM 4MHZ 84-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11K1CFN4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Type
ROMless
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-

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Price
Part Number:
MC68HC11K1CFN4
Manufacturer:
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Part Number:
MC68HC11K1CFN4
Manufacturer:
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Quantity:
10 000
Central Processor Unit (CPU)
Technical Data
62
Mnemonic
TST (opr)
XGDX
XGDY
TSTA
TSTB
TPA
TSX
TSY
TXS
TYS
WAI
Cycle
*
**
Operands
dd
ff
hh
ii
jj
kk
ll
mm
rr
Operators
( )
+
:
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
= High-order byte of 16-bit extended address
= One byte of immediate data
= High-order byte of 16-bit immediate data
= Low-order byte of 16-bit immediate data
= Low-order byte of 16-bit extended address
= 8-bit mask (set bits to be affected)
= Signed relative offset $80 (–128) to $7F (+127)
Contents of register shown inside parentheses
Is transferred to
Is pulled from stack
Is pushed onto stack
Boolean AND
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
Exclusive-OR
Multiply
Concatenation
Arithmetic subtraction symbol or negation symbol (two’s complement)
Test for Zero or
Test A for Zero
Test B for Zero
Transfer Stack
Transfer Stack
Stack Pointer
Stack Pointer
Register to A
Transfer X to
Transfer Y to
Transfer CC
Exchange D
Exchange D
Pointer to X
Pointer to Y
Operation
or Minus
or Minus
Interrupt
(offset relative to address following machine code offset byte))
Wait for
Minus
with X
with Y
Stack Regs & WAIT
IX
IY
Description
SP + 1
SP + 1
IX – 1
IY – 1
CCR
M – 0
A – 0
B – 0
D, D
D, D
Table 3-1. Instruction Set (Sheet 7 of 7)
Freescale Semiconductor, Inc.
SP
SP
For More Information On This Product,
A
IX
IY
IX
IY
A
B
Central Processor Unit (CPU)
Addressing
Go to: www.freescale.com
Mode
INH
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
INH
INH
INH
18
18
18
18
Opcode
07
7D
6D
6D
4D
5D
30
30
35
35
3E
8F
8F
Instruction
hh ll
ff
ff
Operand
Condition Codes
0
1
Cycles
Bit not changed
Bit always cleared
Bit always set
Bit cleared or set, depending on operation
Bit can be cleared, cannot become set
**
2
6
6
7
2
2
3
4
3
4
3
4
S
X
H
Condition Codes
I
M68HC11K Family
N
MOTOROLA
Z
V
0
0
0
C
0
0
0

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