MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 200
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Serial Communications Interface (SCI)
FE — Receiver Framing Error Bit
PE — Receiver Parity Error Bit
18.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
BKF — Break Flag Bit
RPF — Reception in Progress Flag Bit
200
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
a SCI receiver CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading
SCS1 with PE set and then reading the SCDR. Reset clears the PE bit.
•
•
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after 1s appear on the RxD pin followed by
another break character. Reset clears the BKF bit.
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character.
Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is
in progress.
1 = Framing error detected
0 = No framing error detected
1 = Parity error detected
0 = No parity error detected
1 = Break character detected
0 = No break character detected
1 = Reception in progress
0 = No reception in progress
Break character detected
Incoming data
Address:
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$0017
Bit 7
0
0
Figure 18-16. SCI Status Register 2 (SCS2)
= Unimplemented
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
BKF
1
0
Freescale Semiconductor
Bit 0
RPF
0
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