MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 57
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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The FLASH Programming Algorithm Flowchart is shown in
Freescale Semiconductor
10. Clear the PGM bit.
11. Wait for time, t
12. Clear the HVEN bit.
13. Wait for a time, t
3. Write to any FLASH-1 address within the row address range desired with any data.
4. Wait for time, t
5. Set the HVEN bit.
6. Wait for time, t
7. Write data byte to the FLASH-1 address to be programmed.
8. Wait for time, t
9. Repeat step 7 and 8 until all the bytes within the row are programmed.
A. Programming and erasing of FLASH locations can not be performed by
code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address within
the FLASH array memory space such as the COP Control Register
(COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
D. Do not exceed t
cumulative high voltage programming time to the same row before next
erase. t
max. Please also see
E. The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH address programmed to clearing the PGM bit
(step 7 to step 10) must not exceed the maximum programming time, t
max.
F. Be cautious when programming the FLASH-1 array to ensure that
non-FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm or
the byte to be programmed in step 7 of the algorithm. This applies
particularly to:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$FFD2-$FFD3 and $FFDA-$FFFF: Vector area on
NVS
PGS
NVH
PROG
$FFCC-$FFFF: Vector area on MC68HC908AZ60A (52 bytes)
HV
RCV
.
must satisfy this condition: t
MC68HC908AS60A (40 bytes)
.
.
, after which the memory can be accessed in normal read mode.
.
PROG
28.1.14 FLASH Memory
maximum or t
NOTE
NVS
HV
+ t
maximum. t
NVH
Figure
+ t
Characteristics.
PGS
4-4.
HV
+ (t
is defined as the
PROG
X 64)
FLASH-1 Program Operation
≤
PROG
t
HV
57
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