MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 221
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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19.12.5 V
V
reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin
of the slave to the V
19.13 I/O Registers
Three registers control and monitor SPI operation:
19.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
Freescale Semiconductor
SS
•
•
•
•
•
•
•
•
•
This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR
bit.
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
19-4
CPOL bits. Reset clears the CPOL bit.
is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
SPI control register (SPCR $0010)
SPI status and control register (SPSCR $0011)
SPI data register (SPDR $0012)
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
and
SS
Figure
Address:
(Clock Ground)
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
19-5.) To transmit data between SPI modules, the SPI modules must have identical
SS
pin.
SPRIE
$0010
Bit 7
R
0
Figure 19-12. SPI Control Register (SPCR)
= Reserved
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
SPWOM
2
0
SPE
1
0
SPTIE
Bit 0
0
I/O Registers
Figure
221
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