MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 201
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MC908AZ60ACFU
Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AZ60ACFUER.pdf
(414 pages)
Specifications of MC908AZ60ACFU
Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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18.8.6 SCI Data Register
The SCI data register is the buffer between the internal data bus and the receive and transmit shift
registers. Reset has no effect on data in the SCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
18.8.7 SCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the transmitter.
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
SCR2–SCR0 — SCI Baud Rate Select Bits
Freescale Semiconductor
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
These read/write bits select the baud rate prescaler divisor as shown in
and SCP0.
These read/write bits select the SCI baud rate divisor as shown in
SCR2–SCR0.
Address:
Address:
Do not use read-modify-write instructions on the SCI data register.
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$0018
$0019
Bit 7
Bit 7
R7
T7
0
0
Figure 18-18. SCI Baud Rate Register (SCBR)
SCP[1:0]
= Unimplemented
00
01
10
11
Figure 18-17. SCI Data Register (SCDR)
Table 18-9. SCI Baud Rate Prescaling
R6
T6
6
6
0
0
SCP1
R5
T5
5
5
0
NOTE
Unaffected by Reset
SCP0
R4
T4
R
4
4
0
Prescaler Divisor (PD)
= Reserved
R3
T3
R
3
3
0
13
1
3
4
SCR2
R2
T2
2
2
0
Table
Table
18-10. Reset clears
SCR1
R1
T1
1
1
0
18-9. Reset clears SCP1
SCR0
Bit 0
Bit 0
R0
T0
0
I/O Registers
201
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