M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 102

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 46 Timing requirements in memory expansion mode and microprocessor mode
(V
Table 47 Switching characteristics in memory expansion mode and microprocessor mode
(V
Note: The RESET
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d
CC
su
h
su
h
su
h
su
h
CC
C
WH
WL
d
d
V
V
d
V
d
V
WL
d
d
V
V
d
V
V
( -AH)
( -AL)
( -SYNC)
( -DB)
(AH-RD), t
(AL-RD), t
(WR-DB)
(RESET-RESET
( -RESET
( )
( -AH)
( -AL)
( -SYNC)
( -DB)
(RD-AH), t
(RD-AL), t
(WR-DB)
( -ONW)
( -DB)
(RD-ONW), t
(RD-DB)
(ONW- )
(DB- )
(ONW-RD), t
(DB-RD)
( )
(RD), t
( )
= 4.0 to 5.5 V, V
= 4.0 to 5.5 V, V
input goes “H”.
Symbol
WL
Symbol
d
V
OUT
d
V
(WR)
(AL-WR)
(AH-WR)
(WR-AL)
(WR-AH)
OUT
h
)
su
(WR-ONW)
OUT
(ONW-WR)
output goes “H” in synchronized with the rise of the
SS
SS
)
= 0 V, T
= 0 V, T
AD
AD
AD
AD
SYNC delay time
SYNC valid time
Data bus delay time
Data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
AD
AD
AD
AD
Data bus delay time
Data bus valid time
RESET
RESET
clock cycle time
clock “H” pulse width
clock “L” pulse width
15
7
15
7
15
7
15
7
–AD
–AD
–AD
–AD
a
a
–AD
–AD
–AD
–AD
= –20 to 85 °C, in high-speed mode, unless otherwise noted)
= –20 to 85 °C, in high-speed mode, unless otherwise noted)
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
ONW input setup time
ONW input hold time
Data bus setup time
Data bus hold time
OUT
OUT
0
0
0
0
8
8
8
8
delay time
valid time
delay time
valid time
delay time
delay time
valid time
valid time
output delay time
output valid time (Note)
Parameter
Parameter
conditions
clock that is anywhere between a few cycles and 10-several cycles after RESET
Fig. 83
Test
3t
t
t
t
t
t
C
C
C
C
C
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
C
(X
(X
(X
(X
(X
(X
Min.
10
10
IN
IN
IN
IN
IN
2
2
2
2
0
IN
)–10
)–10
)–10
)–35
)–40
)–10
MITSUBISHI MICROCOMPUTERS
Min.
–20
–20
–20
–20
50
50
0
0
Limits
t
t
C
C
2t
(X
(X
C
Limits
Typ.
16
20
16
15
15
Typ.
IN
IN
(X
5
5
5
5
5
)–16
)–20
IN
)
3886 Group
Max.
Max.
200
100
35
40
30
30
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
99