M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 44

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

[I
The I
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the S
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the S
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 cycles of
the rising of the S
The I
I
the I
struction to the I
the MST bit of the I
S
Reading data from the I
gardless of the ES0 bit value.
[I
The I
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition is detected.
•Bit 0: Read/write bit (RBW)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RBW) of the I
ister.
The RBW bit is cleared to “0” automatically when the stop condi-
tion is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
2
CL
C-BUS interface enable bit (ES0 bit : bit 3 of address 15
2
2
C Data Shift Register (S0)] 0012
C Address Register (S0D)] 0013
2
is output by a write instruction to the I
2
2
2
C control register is “1.” The bit counter is reset by a write in-
C data shift register is in a write enable status only when the
C address register (address 0013
C data shift register (S0 : address 0012
2
C data shift register. When both the ES0 bit and
CL
2
C status register (address 0014
clock until input to this register.
2
C data shift register is always enabled re-
16
) consists of a 7-bit slave
2
C data shift register.
16
are required from
16
16
) is an 8-bit shift
2
C address reg-
16
CL
CL
) are “1,” the
clock, and
clock, and
16
) of
Fig. 36 Structure of I
S A D 6 S A D 5 S A D 4 S A D 3 S A D 2 S A D 1 S A D 0 R B W
b 7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
2
C address register
b0
I
( S 0 D : a d d r e s s 0 0 1 3
3886 Group
2
R e a d / w r i t e b i t
S l a v e a d d r e s s
C a d d r e s s r e g i s t e r
1 6
)
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