M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 58

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 001E
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
001E
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 001E
started before an underflow. When the watchdog timer control reg-
ister (address 001E
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register (address
001E
Fig. 53 Block diagram of Watchdog timer
Fig. 54 Structure of Watchdog timer control register
16
16
X
) and an internal reset occurs at an underflow of the watch-
), each watchdog timer H and L is set to “FF
CIN
X
Main clock division
ratio selection bits
(Note)
IN
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
RESET
16
16
) after resetting, the watchdog timer is in the
) is read, the values of the high-order 6 bits
STP instruction disable bit
“10”
“00”
“01”
b 7
STP instruction
“FF
watchdog timer
control register is
written to.
1/16
16
” is set when
Watchdog timer L (8)
16
.”
16
) may be
b 0
Bit 7 of the watchdog timer control register (address 001E
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to f(X
at 8 MHz frequency and f(X
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(X
is set to f(X
32 kHz frequency. This bit is cleared to “0” after resetting.
Bit 6 of the watchdog timer control register (address 001E
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal reset occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
“0”
“1”
W a t c h d o g t i m e r c o n t r o l r e g i s t e r
( W D T C O N : a d d r e s s 0 0 1 E
Watchdog timer H count
source selection bit
Watchdog timer H count source selection bit operation
Operation of STP instruction disable bit
W a t c h d o g t i m e r H ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t )
S T P i n s t r u c t i o n d i s a b l e b i t
0 : S T P i n s t r u c t i o n e n a b l e d
1 : S T P i n s t r u c t i o n d i s a b l e d
W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c t i o n b i t
0 : W a t c h d o g t i m e r L u n d e r f l o w
1 : f ( X
I N
) / 1 6 o r f ( X
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
IN
)= 512 s at 8 MHz frequency and f(X
Watchdog timer H (8)
C I N
Reset
circuit
IN
) / 1 6
MITSUBISHI MICROCOMPUTERS
) (or f(X
CIN
1 6
CIN
)
)=32.768 s at 32 kHz frequency.
)). The detection time in this case
Data bus
3886 Group
Internal reset
“FF
watchdog timer
control register is
written to.
16
” is set when
IN
CIN
)=131.072 ms
)=128 ms at
16
16
) per-
) per-
55