M38869FFAHP Renesas Electronics America, M38869FFAHP Datasheet - Page 54

• Manufacturer Part Number: M38869FFAHP
• Description: IC 740 MCU FLASH 61K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38869FFAHP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

A-D CONVERTER
[A-D Conversion Register 1,2 (AD1, AD2)]
0035
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Bit 7 of the A-D conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A-D converter becomes
the 10-bit A-D mode. When this bit is set to “1,” that becomes the
8-bit A-D mode. The conversion result of the 8-bit A-D mode is
stored in the A-D conversion register 1. As for 10-bit A-D mode,
10-bit reading or 8-bit reading can be performed by selecting the
reading procedure of the A-D conversion register 1, 2 after A-D
conversion is completed (in Figure 48).
The A-D conversion register 1 performs the 8-bit reading inclined
to MSB after reset, the A-D conversion is started, or reading of the
A-D converter register 1 is generated; and the register becomes
the 8-bit reading inclined to LSB after the A-D converter register 2
is generated.
[AD/DA Control Register (ADCON)] 0034
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
10-bit A-D mode (256 division in 8-bit A-D mode).
The A-D converter successively compares the comparison voltage
V
voltage.
• 10-bit A-D mode (10-bit reading)
• 10-bit A-D mode (8-bit reading)
• 8-bit A-D mode
V
V
V
ref
ref
ref
ref
SS
in each mode, dividing the V
=
=
=
=0
and V
16
V
V
1024
V
256
256
REF
REF
REF
, 0038
REF
n (n = 0–1023)
n (n = 0–255)
(n–0.5) (n = 1–255)
into 1024, and outputs the divided voltages in the
16
(n = 0)
REF
(see below), with the input
16
Channel Selector
The channel selector selects one of ports P6
and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
A-D conversion registers 1, 2. When an A-D conversion is com-
pleted, the control circuit sets the A-D conversion completion bit
and the A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
Fig. 47 Structure of AD/DA control register
Fig. 48 Structure of 10-bit A-D mode reading
N o t e : B i t s 2 t o 6 o f a d d r e s s 0 0 3 8
1 0 - b i t r e a d i n g
8 - b i t r e a d i n g ( R e a d o n l y a d d r e s s 0 0 3 5
b 7
( R e a d a d d r e s s 0 0 3 8
( A d d r e s s 0 0 3 8
( A d d r e s s 0 0 3 5
( A d d r e s s 0 0 3 5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
IN
) to 500 kHz or more during an A-D conversion.
MITSUBISHI MICROCOMPUTERS
1 6
1 6
1 6
b 0
)
)
)
A D / D A c o n t r o l r e g i s t e r
( A D C O N : a d d r e s s 0 0 3 4
A n a l o g i n p u t p i n s e l e c t i o n b i t s
A - D c o n v e r s i o n c o m p l e t i o n b i t
P W M
P W M
D A 1 o u t p u t e n a b l e b i t
1 : D A 1 o u t p u t e n a b l e d
D A 2 o u t p u t e n a b l e b i t
b 7
b 7
b 7
b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2
0
1 6
b 2 b 1 b 0
0 0 0 : P 6
0 0 1 : P 6
0 1 0 : P 6
0 1 1 : P 6
1 0 0 : P 6
1 0 1 : P 6
1 1 0 : P 6
1 1 1 : P 6
0 : C o n v e r s i o n i n p r o g r e s s
1 : C o n v e r s i o n c o m p l e t e d
0 : P 5
1 : P 3
0 : P 5
1 : P 3
0 : D A 1 o u t p u t d i s a b l e d
0 : D A 2 o u t p u t d i s a b l e d
1 : D A 2 o u t p u t e n a b l e d
0
1
1 6
b e f o r e 0 0 3 5
o u t p u t p i n s e l e c t i o n b i t
o u t p u t p i n s e l e c t i o n b i t
b e c o m e s “ 0 ” a t r e a d i n g .
6
0
7
1
/ P W M
/ P W M
/ P W M
/ P W M
3886 Group
0
1
2
3
4
5
6
7
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
/ A N
0 1
0 0
1 1
1 0
0
1
2
3
4
5
6
7
0
/AN
1 6
1 6
0
)
b 9
1 6
)
to P6
)
b 0
b 8
b 0
b 0
7
/AN
51
7
,