M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet
M306N5FCTFP
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M306N5FCTFP Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M16C/6N Group (M16C/6N5) 16 Hardware Manual Renesas MCU M16C Family / M16C/60 Series All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Electronics Corp. ...
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Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Blank: Set according to the application 0 : Set to ...
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List of Abbreviations and Acronyms Abbreviation ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi-Z High Impedance IEBus Inter ...
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SFR Page Reference ............................................................................................................ B-1 1. Overview ............................................................................................................................... 1 1.1 Applications .................................................................................................................................................. 1 1.2 Performance Overview ................................................................................................................................ 2 1.3 Block Diagram .............................................................................................................................................. 3 1.4 Product Information ...................................................................................................................................... 4 1.5 Pin Assignments .......................................................................................................................................... 5 1.6 Pin Functions ............................................................................................................................................... 9 2. Central ...
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Bus Control ................................................................................................................................................ 36 7.2.1 Address Bus ....................................................................................................................................... 36 7.2.2 Data Bus ............................................................................................................................................ 36 7.2.3 Chip Select Signal .............................................................................................................................. 36 7.2.4 Read and Write Signals ..................................................................................................................... 38 7.2.5 ALE Signal ......................................................................................................................................... 38 ________ 7.2.6 RDY Signal ........................................................................................................................................ 39 __________ ...
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Interrupt Sequence .......................................................................................................................... 78 10.5.5 Interrupt Response Time .................................................................................................................. 79 10.5.6 Variation of IPL when Interrupt Request is Accepted ....................................................................... 79 10.5.7 Saving Registers .............................................................................................................................. 80 10.5.8 Returning from Interrupt Routine ..................................................................................................... 81 10.5.9 Interrupt Priority ............................................................................................................................... 81 10.5.10 ...
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A/D Converter .................................................................................................................. 188 16.1 Mode Description ................................................................................................................................... 192 16.1.1 One-shot Mode .............................................................................................................................. 192 16.1.2 Repeat Mode ................................................................................................................................. 194 16.1.3 Single Sweep Mode ....................................................................................................................... 196 16.1.4 Repeat Sweep Mode 0 .................................................................................................................. 198 16.1.5 Repeat Sweep Mode 1 .................................................................................................................. 200 ...
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Programmable I/O Ports ................................................................................................. 234 20.1 PDi Register ........................................................................................................................................... 234 20.2 Pi Register ............................................................................................................................................. 234 20.3 PURj Register ........................................................................................................................................ 234 20.4 PCR Register ......................................................................................................................................... 235 21. Flash Memory Version .................................................................................................... 247 21.1 Memory Map .......................................................................................................................................... 248 21.1.1 Boot Mode ...
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DMAC .................................................................................................................................................... 347 23.7.1 Write to DMAE Bit in DMiCON Register ........................................................................................ 347 23.8 Timers .................................................................................................................................................... 348 23.8.1 Timer A ........................................................................................................................................... 348 23.8.2 Timer B ........................................................................................................................................... 351 23.9 Serial Interface ....................................................................................................................................... 353 23.9.1 Clock Synchronous Serial I/O Mode .............................................................................................. ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Chip Select Control Register 0009h Address Match Interrupt ...
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Address Register 0080h 0081h 0082h CAN0 Message Box 2: Identifier / DLC 0083h 0084h 0085h 0086h 0087h 0088h 0089h CAN0 Message Box 2: Data Field 008Ah 008Bh 008Ch 008Dh 008Eh CAN0 Message Box 2: Time Stamp 008Fh 0090h 0091h 0092h ...
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Address Register 0100h 0101h 0102h CAN0 Message Box 10: Identifier / DLC 0103h 0104h 0105h 0106h 0107h 0108h 0109h CAN0 Message Box 10: Data Field 010Ah 010Bh 010Ch 010Dh 010Eh CAN0 Message Box 10: Time Stamp 010Fh 0110h 0111h 0112h ...
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Address Register 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h ...
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Address Register 0200h CAN0 Message Control Register 0 0201h CAN0 Message Control Register 1 0202h CAN0 Message Control Register 2 0203h CAN0 Message Control Register 3 0204h CAN0 Message Control Register 4 0205h CAN0 Message Control Register 5 0206h CAN0 ...
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Address Register 0380h Count Start Flag 0381h Clock Prescaler Reset Flag 0382h One-Shot Start Flag 0383h Trigger Select Register 0384h Up/Down Flag 0385h 0386h Timer A0 Register 0387h 0388h Timer A1 Register 0389h 038Ah Timer A2 Register 038Bh 038Ch Timer ...
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M16C/6N Group (M16C/6N5) Renesas MCU 1. Overview The M16C/6N Group (M16C/6N5) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These MCUs ...
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M16C/6N Group (M16C/6N5) 1.2 Performance Overview Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N5). Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N5) Item CPU Number of fundamental instructions Minimum instruction execution time Operating mode Address space ...
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M16C/6N Group (M16C/6N5) 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 Port P0 Internal peripheral functions Timer (16 bits) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Watchdog timer (15 bits) DMAC (2 channels) ...
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... M16C/6N Group (M16C/6N5) 1.4 Product Information Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages. Table 1.2 Product Information Type No. M306N5FCFP M306N5FCGP M306N5FCTFP M306N5FCTGP M306N5FCVFP M306N5FCVGP M306N5MC-XXXGP M306N5MCT-XXXFP M306N5MCT-XXXGP M306N5MCV-XXXFP M306N5MCV-XXXGP NOTES: 1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A). ...
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M16C/6N Group (M16C/6N5) 1.5 Pin Assignments Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names. NOTE: 1. P7_1 and P9_1 are N channel open-drain pins. Figure 1.3 Pin Assignments ...
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M16C/6N Group (M16C/6N5) P1_2/D10 76 P1_1/D9 77 P1_0/ P0_7/AN0_7/D7 P0_6/AN0_6/D6 80 P0_5/AN0_5/D5 81 P0_4/AN0_4/ P0_3/AN0_3/D3 84 P0_2/AN0_2/D2 85 P0_1/AN0_1/D1 86 P0_0/AN0_0/D0 87 P10_7/AN7/KI3 88 P10_6/AN6/KI2 89 P10_5/AN5/KI1 90 P10_4/AN4/KI0 91 P10_3/AN3 92 P10_2/AN2 93 P10_1/AN1 94 ...
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M16C/6N Group (M16C/6N5) Table 1.3 List of Pin Names (1) Pin No. Control Interrupt Port FP GP Pin 1 99 P9_6 2 100 P9_5 3 1 P9_4 4 2 P9_3 5 3 P9_2 6 4 P9_1 7 5 P9_0 8 ...
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M16C/6N Group (M16C/6N5) Table 1.4 List of Pin Names (2) Pin No. Control Interrupt Port FP GP Pin 51 49 P4_3 52 50 P4_2 53 51 P4_1 54 52 P4_0 55 53 P3_7 56 54 P3_6 57 55 P3_5 58 ...
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M16C/6N Group (M16C/6N5) 1.6 Pin Functions Tables 1.5 to 1.7 list the Pin Functions. Table 1.5 Pin Functions (1) Signal Name Pin Name Power supply VCC1, VCC2, VSS input AVCC, AVSS Analog power supply input _____________ Reset input RESET CNVSS ...
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M16C/6N Group (M16C/6N5) Table 1.6 Pin Functions (2) Signal Name Pin Name Main clock XIN input Main clock XOUT output Sub clock XCIN input Sub clock XCOUT output BCLK output BCLK Clock output CLKOUT ________ ________ INT interrupt input INT0 ...
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M16C/6N Group (M16C/6N5) Table 1.7 Pin Functions (3) Signal Name Pin Name I/O port P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to ...
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M16C/6N Group (M16C/6N5) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two register banks. b31 R2 ...
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M16C/6N Group (M16C/6N5) 2.3 Frame Base Register (FB configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector ...
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M16C/6N Group (M16C/6N5) 3. Memory Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a ...
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M16C/6N Group (M16C/6N5) 4. Special Function Registers (SFRs) An SFR (Special Function Register control register for a peripheral function. Tables 4.1 to 4.12 list the SFR Information. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h 0003h (1) ...
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M16C/6N Group (M16C/6N5) Table 4.2 SFR Information (2) Address 0040h 0041h CAN0 Wake-up Interrupt Control Register 0042h CAN0 Successful Reception Interrupt Control Register 0043h CAN0 Successful Transmission Interrupt Control Register 0044h INT3 Interrupt Control Register 0045h Timer B5 Interrupt Control ...
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M16C/6N Group (M16C/6N5) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h CAN0 Message Box 2: Identifier / DLC 0083h 0084h 0085h 0086h 0087h 0088h 0089h CAN0 Message Box 2: Data Field 008Ah 008Bh 008Ch 008Dh 008Eh CAN0 Message Box ...
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M16C/6N Group (M16C/6N5) Table 4.4 SFR Information (4) Address 00C0h 00C1h 00C2h CAN0 Message Box 6: Identifier / DLC 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h CAN0 Message Box 6: Data Field 00CAh 00CBh 00CCh 00CDh 00CEh CAN0 Message Box ...
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M16C/6N Group (M16C/6N5) Table 4.5 SFR Information (5) Address 0100h 0101h 0102h CAN0 Message Box 10: Identifier / DLC 0103h 0104h 0105h 0106h 0107h 0108h 0109h CAN0 Message Box 10: Data Field 010Ah 010Bh 010Ch 010Dh 010Eh CAN0 Message Box ...
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M16C/6N Group (M16C/6N5) Table 4.6 SFR Information (6) Address 0140h 0141h 0142h CAN0 Message Box 14: Identifier /DLC 0143h 0144h 0145h 0146h 0147h 0148h 0149h CAN0 Message Box 14: Data Field 014Ah 014Bh 014Ch 014Dh 014Eh CAN0 Message Box 14: ...
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M16C/6N Group (M16C/6N5) Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh ...
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M16C/6N Group (M16C/6N5) Table 4.8 SFR Information (8) Address 01C0h Timer B3, B4, B5 Count Start Flag 01C1h 01C2h Timer A1-1 Register 01C3h 01C4h Timer A2-1 Register 01C5h 01C6h Timer A4-1 Register 01C7h Three-Phase PWM Control Register 0 01C8h Three-Phase ...
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M16C/6N Group (M16C/6N5) Table 4.9 SFR Information (9) Address 0200h CAN0 Message Control Register 0 CAN0 Message Control Register 1 0201h CAN0 Message Control Register 2 0202h CAN0 Message Control Register 3 0203h CAN0 Message Control Register 4 0204h CAN0 ...
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M16C/6N Group (M16C/6N5) Table 4.10 SFR Information (10) Address 0240h 0241h 0242h CAN0 Acceptance Filter Support Register 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h ...
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M16C/6N Group (M16C/6N5) Table 4.11 SFR Information (11) Address 0380h Count Start Flag 0381h Clock Prescaler Reset Flag One-Shot Start Flag 0382h 0383h Trigger Select Register Up/Down Flag 0384h 0385h 0386h Timer A0 Register 0387h 0388h Timer A1 Register 0389h ...
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M16C/6N Group (M16C/6N5) Table 4.12 SFR Information (12) Address 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h A/D Register 3 03C7h 03C8h A/D Register 4 03C9h 03CAh A/D Register 5 03CBh 03CCh ...
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M16C/6N Group (M16C/6N5) 5. Resets Hardware reset, software reset, watchdog timer reset, and oscillation stop detection reset are available to reset the MCU. 5.1 Hardware Reset The MCU resets pins, the CPU and SFR by setting the RESET pin. If ...
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M16C/6N Group (M16C/6N5) VCC XIN td(P-R) More than 20 cycles are needed RESET BCLK Microprocessor mode BYTE = H Address RD WR CS0 Microprocessor mode BYTE = L Address RD WR CS0 Single-chip mode Addres s Figure 5.2 Reset Sequence ...
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M16C/6N Group (M16C/6N5) 5.2 Software Reset The MCU resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to 1 (MCU reset). Then the MCU executes the program in an address determined by the ...
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M16C/6N Group (M16C/6N5) 6. Processor Mode 6.1 Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion mode, and microprocessor mode. Table 6.1 shows the Features of Processor Modes. Table 6.1 Features of Processor ...
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M16C/6N Group (M16C/6N5) Processor Mode Register NOTES: 1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). 2. Bits PM01 to PM00 do not ...
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M16C/6N Group (M16C/6N5) Processor Mode Register NOTES: 1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). 2. For the ...
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M16C/6N Group (M16C/6N5) Single-chip mode 00000h SFR 00400h Internal RAM XXXXXh Cannot use YYYYYh Internal ROM FFFFFh NOTES: 1. M16C/6N Group (M16C/6N5) has no device model expanded over 192 Kbytes of the internal ROM. Accrdingly, the PM13 bit is set ...
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M16C/6N Group (M16C/6N5) When PM13 = 0 and PM10 = 0 Memory expansion mode 00000h 00400h Internal RAM XXXXXh Reserved area 04000h 08000h 27000h Reserved area 28000h 30000h External area 80000h Reserved area YYYYYh Internal ROM FFFFFh Internal RAM Capacity ...
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M16C/6N Group (M16C/6N5) 7. Bus During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/output to and from external devices. These bus control pins include A0 to A19 D15, CS0 ...
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M16C/6N Group (M16C/6N5) 7.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 7.2.1 Address Bus The address bus consists of 20 lines A19. The address bus width can ...
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M16C/6N Group (M16C/6N5) Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi. The address bus and the chip select signal both change state between these two cycles. ...
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M16C/6N Group (M16C/6N5) 7.2.4 Read and Write Signals When the data bus is 16-bit width, the read and write signals can be chosen combination of RD, ______ ________ WR, and BHE or a combination of RD, WRL, ...
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M16C/6N Group (M16C/6N5) ________ 7.2.6 RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on ________ the RDY pin is asserted low at the last falling edge of BCLK ...
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M16C/6N Group (M16C/6N5) __________ 7.2.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the __________ input on HOLD pin is pulled low, the MCU is placed ...
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M16C/6N Group (M16C/6N5) Table 7.6 Pin Functions for Each Processor Mode Processor Mode Memory Expansion Mode or Microprocessor Mode Bits PM05 to PM04 00b (separate bus) Data bus width 8 bits BYTE pin P0_0 to P0_7 P1_0 ...
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M16C/6N Group (M16C/6N5) 7.2.9 External Bus Status when Internal Area Accessed Table 7.7 shows the External Bus Status When Internal Area Accessed. Table 7.7 External Bus Status When Internal Area Accessed Item A0 to A19 Address output D0 to D15 ...
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M16C/6N Group (M16C/6N5) Table 7.8 Software Wait Related Bits and Bus Cycles PM2 Register Area Bus Mode PM20 Bit SFR - Internal - - ROM, RAM - - External Separate - area bus - - - - ...
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M16C/6N Group (M16C/6N5) (1) Separate bus, No wait setting BCLK Write signal Read signal Data bus Address bus CS (2) Separate bus, 1-wait setting BCLK Write signal Read signal Data bus Address bus CS (3) Separate bus, 2-wait setting BCLK ...
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M16C/6N Group (M16C/6N5) (1) Separate bus, 3-wait setting BCLK Write signal Read signal Data bus Address bus CS (2)Multiplexed bus 2-wait setting BCLK Write signal Read signal ALE Address bus Address bus/ Data bus Address CS (3)Multiplexed bus, ...
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M16C/6N Group (M16C/6N5) 8. Clock Generation Circuit 8.1 Types of Clock Generation Circuit Four circuits are incorporated to generate the system clock signal: • Main clock oscillation circuit • Sub clock oscillation circuit • On-chip oscillator • PLL frequency synthesizer ...
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M16C/6N Group (M16C/6N5) Sub clock oscillation circuit XCIN CM04 CM10 XIN (stop mode) R Main clock CM05 oscillation circuit S Q WAIT instruction R RESET Software reset NMI Interrupt request level judgment output PM00, PM01 CM00, CM01, CM02, ...
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M16C/6N Group (M16C/6N5) System Clock Control Register NOTES: 1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled). 2. The fC32 clock does not ...
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M16C/6N Group (M16C/6N5) System Clock Control Register NOTES: 1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled the ...
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M16C/6N Group (M16C/6N5) Oscillation Stop Detection Register NOTES: 1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled). 2. Bits CM20, CM21, and ...
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M16C/6N Group (M16C/6N5) Peripheral Clock Select Register NOTE: 1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled). Figure ...
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M16C/6N Group (M16C/6N5) Processor Mode Register NOTES: 1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enable). 2. The PM20 bit ...
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M16C/6N Group (M16C/6N5) The following describes the clocks generated by the clock generation circuit. 8.1.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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M16C/6N Group (M16C/6N5) 8.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. ...
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M16C/6N Group (M16C/6N5) 8.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in ...
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M16C/6N Group (M16C/6N5) Set the CM07 bit to 0 (main clock), bits CM17 to CM16 to 00b (main clock undivided), and the CM06 bit to 0 (bits CM16 and CM17 enabled). Set the CM11 bit to 1 (PLL clock for ...
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M16C/6N Group (M16C/6N5) 8.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 8.2.1 CPU Clock and BCLK These are operating clocks for the CPU ...
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M16C/6N Group (M16C/6N5) 8.4 Power Control Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this document. 8.4.1 Normal ...
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M16C/6N Group (M16C/6N5) 8.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the ...
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M16C/6N Group (M16C/6N5) 8.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is 1 ...
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M16C/6N Group (M16C/6N5) Table 8.5 Interrupts to Exit Wait Mode and Use Conditions Interrupt _______ NMI interrupt Serial interface interrupt Key input interrupt A/D conversion interrupt Timer A interrupt Timer B interrupt ______ INT interrupt CAN0 wake-up interrupt If the ...
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M16C/6N Group (M16C/6N5) 8.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least ...
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M16C/6N Group (M16C/6N5) 8.4.3.3 Exiting Stop Mode Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt. When the hardware reset or NMI interrupt is used to exit stop mode, set all ILVL2 to ILVL0 bits ...
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M16C/6N Group (M16C/6N5) Figure 8.12 shows the State Transition to Stop Mode and Wait Mode. Figure 8.13 shows the State Transition in Normal Operating Mode. Table 8.8 shows a state transition matrix describing allowed transition and setting. The vertical line ...
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M16C/6N Group (M16C/6N5) Main clock oscillation PLL operating mode High-speed mode PLC07 = 1 CPU clock CPU clock CM11 = 1 (6) : f(PLL) : f(XIN) CM07 = 0 CM07 = 0 CM06 = 0 CM06 = 0 PLC07 = ...
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M16C/6N Group (M16C/6N5) Table 8.8 Allowed Transition and Setting High-Speed Mode, Low-Speed Low Power PLL Operating On-chip Oscillator On-chip Oscillator Medium-Speed Mode High-speed mode, (NOTE 8) medium-speed mode Low-speed (8) (2) mode Low power - dissipation mode PLL operating (12) ...
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M16C/6N Group (M16C/6N5) 8.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection ...
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M16C/6N Group (M16C/6N5) 8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are ...
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M16C/6N Group (M16C/6N5) 9. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 9.1 shows the PRCR Register. The registers protected by the ...
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M16C/6N Group (M16C/6N5) 10. Interrupts 10.1 Type of Interrupts Figure 10.1 shows the Types of Interrupts. Software (Non-maskable interrupt) Interrupt Hardware NOTES: 1. The peripheral functions in the MCU are used to generate the peripheral interrupt not normally ...
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M16C/6N Group (M16C/6N5) 10.2 Software Interrupts A software interrupt is generated when executing certain instructions. Software interrupts are non- maskable interrupts. 10.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when executing the UND instruction. 10.2.2 Overflow Interrupt An ...
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M16C/6N Group (M16C/6N5) 10.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 10.3.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 10.3.1.1 NMI Interrupt _______ An NMI interrupt is generated when input ...
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M16C/6N Group (M16C/6N5) 10.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address ...
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M16C/6N Group (M16C/6N5) 10.4.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector table area. Table 10.2 lists the Relocatable Vector Tables. Setting an even address in the INTB ...
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M16C/6N Group (M16C/6N5) 10.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts. Use the I ...
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M16C/6N Group (M16C/6N5) Interrupt Control Register Bit Symbol NOTES rewrite the interrupt control registers point that does not generate the interrupt request for that register. ...
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M16C/6N Group (M16C/6N5) 10.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts. 10.5.2 IR Bit ...
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M16C/6N Group (M16C/6N5) 10.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here interrupt request is ...
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M16C/6N Group (M16C/6N5) 10.5.5 Interrupt Response Time Figure 10.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine ...
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M16C/6N Group (M16C/6N5) 10.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in ...
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M16C/6N Group (M16C/6N5) 10.5.8 Returning from Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of ...
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M16C/6N Group (M16C/6N5) Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 UART1 reception, ACK1 UART0 reception, ACK0 UART2 reception, ACK2 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer A0 UART1 transmission, NACK1 UART0 ...
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M16C/6N Group (M16C/6N5) ______ 10.6 INT Interrupt _______ INTi interrupt ( triggered by the edges of external inputs. The edge polarity is selected using bits IFSR10 to IFSR15 in the IFSR1 register. ________ INT4 share ...
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M16C/6N Group (M16C/6N5) Interrupt Request Cause Select Register NOTES: 1.Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using the timer B3 interrupt, ...
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M16C/6N Group (M16C/6N5) ______ 10.7 NMI Interrupt _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI ...
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M16C/6N Group (M16C/6N5) 10.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register ( 3). Set the start address of any instruction in ...
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M16C/6N Group (M16C/6N5) Address Match Interrupt Enable Register Address Match Interrupt Enable Register Address Match Interrupt Register ...
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M16C/6N Group (M16C/6N5) 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit ...
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M16C/6N Group (M16C/6N5) Watchdog Timer Control Register Watchdog Timer Start Register b7 b0 The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog ...
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M16C/6N Group (M16C/6N5) 12. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from ...
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M16C/6N Group (M16C/6N5) Table 12.1 DMAC Specifications Item No. of channels Transfer memory space Maximum no. of bytes transferred 128 Kbytes (with 16-bit transfer Kbytes (with 8-bit transfer) (1) (2) DMA request sources Channel priority Transfer unit Transfer ...
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M16C/6N Group (M16C/6N5) DMA0 Request Source Select Register NOTE: 1. The DMA0 request sources can be selected by a combination of the DMS bit and bits DSEL3 to DSEL0 in the manner ...
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M16C/6N Group (M16C/6N5) DMA1 Request Source Select Register NOTE: 1. The DMA1 request sources can be selected by a combination of the DMS bit and bits DSEL3 to DSEL0 in the manner ...
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M16C/6N Group (M16C/6N5) DMAi Source Pointer ( (b23) (b19) (b16) (b15 NOTE the DSD bit in the DMiCON register is 0 (fixed), this register can only be written to when the ...
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M16C/6N Group (M16C/6N5) 12.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source ...
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M16C/6N Group (M16C/6N5) (1) When the transfer unit bits and the source of transfer is an even address BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) When the transfer unit ...
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M16C/6N Group (M16C/6N5) 12.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 12.2 lists the DMA Transfer Cycles. Table 12.3 lists the Coefficient j, k. The number of DMAC transfer cycles ...
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M16C/6N Group (M16C/6N5) 12.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register ( (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the ...
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M16C/6N Group (M16C/6N5) 12.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge ...
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M16C/6N Group (M16C/6N5) 13. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, ...
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M16C/6N Group (M16C/6N5) 1/2 Main clock f1 PLL clock On-chip 1/8 oscillator clock f32 fC32 TCK1 to TCK0 TB0IN TCK1 to TCK0 TB1IN TCK1 to TCK0 00 01 ...
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M16C/6N Group (M16C/6N5) 13.1 Timer A Figure 13.3 shows the Timer A Block Diagram. Figures 13.4 to 13.6 show the timer A-related registers. The timer A supports the following four modes. Except in event counter mode, timers ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( Timer Ai Register ( (b15) (b8 Timer mode Event counter mode One-shot timer ...
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M16C/6N Group (M16C/6N5) Count Start Flag (1) Up/Down Flag NOTES: 1.Use the MOV instruction to write to this register. 2.Make sure the port direction ...
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M16C/6N Group (M16C/6N5) One-Shot Start Flag NOTES: 1.Make sure the PD7_1 bit in the PD7 register is set to 0 (input mode). 2.Overflow or underflow. Trigger Select Register ...
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M16C/6N Group (M16C/6N5) 13.1.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.1 lists the Timer Mode Specifications. Figure 13.7 shows Registers TA0MR to TA4MR in Timer Mode. Table 13.1 Timer Mode Specifications Item ...
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M16C/6N Group (M16C/6N5) 13.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 13.2 lists the ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( (When not using two-phase pulse signal processing Bit Symbol NOTES: 1.During event counter mode, the count source ...
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M16C/6N Group (M16C/6N5) Table 13.3 Event Counter Mode Specifications (when using two-phase pulse signal processing with timers A2, A3, and A4) Item Count source • Two-phase pulse signals input to TAiIN or TAiOUT pins Count operation • Up-count or down-count ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( (When using two-phase pulse signal processing Bit Symbol NOTES: 1. The TCK1 bit is valid ...
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M16C/6N Group (M16C/6N5) 13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in timer A3 ...
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M16C/6N Group (M16C/6N5) 13.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period. Table 13.4 lists the One-shot ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( Bit Symbol NOTES: 1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are ...
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M16C/6N Group (M16C/6N5) 13.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Table 13.5 lists the ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( Bit Symbol NOTES: 1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 00b ...
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M16C/6N Group (M16C/6N5) Count source "H" Input signal to TAiIN pin "L" "H" PWM pulse output from TAiOUT pin "L" IR bit in TAiIC register fj: Frequency of count source (f1, f2, f8, f32, fC32) ...
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M16C/6N Group (M16C/6N5) 13.2 Timer B Figure 13.15 shows a Timer B Block Diagram. Figures 13.16 and 13.17 show the timer B-related registers. Timer B supports the following three modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i ...
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M16C/6N Group (M16C/6N5) Timer Bi Mode Register ( Bit Symbol TMOD0 TMOD1 NOTES: 1. Timers B0 and B3. 2. Timers B1, B2, B4, and B5. Timer Bi Register ...
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M16C/6N Group (M16C/6N5) Count Start Flag Timer B3, B4, B5 Count Start Flag Clock Prescaler Reset Flag ...
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M16C/6N Group (M16C/6N5) 13.2.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 13.6 lists the Timer Mode Specifications. Figure 13.18 shows Registers TB0MR to TB5MR in Timer Mode. Table 13.6 Timer Mode Specifications Item ...
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M16C/6N Group (M16C/6N5) 13.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 13.7 lists the Event Counter Mode Specifications. Figure 13.19 shows Registers TB0MR to ...
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M16C/6N Group (M16C/6N5) 13.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. Table 13.8 lists the Pulse Period and Pulse Width ...
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M16C/6N Group (M16C/6N5) Timer Bi Mode Register ( Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES: 1. This flag is undefined after reset. ...
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M16C/6N Group (M16C/6N5) Count source "H" Measurement pulse "L" Reload register counter transfer timing Timing at which counter reaches 0000h 1 TBiS bit bit in TBiIC register 0 1 MR3 bit in TBiMR register 0 Bits TB0S ...
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M16C/6N Group (M16C/6N5) 14. Three-Phase Motor Control Timer Function Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 14.1 lists the Three-phase Motor Control Timer Function Specifications. Figure 14.1 shows the Three-phase Motor ...
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M16C/6N Group (M16C/6N5) INV00 to INV07: Bits in INVC0 register INV10 to INV15: Bits in INVC1 register DUi, DUBi: Bits in IDBi register ( TA1S to TA4S: Bits in TABSR register PWCON: Bits in TB2SC register INV00 ...
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M16C/6N Group (M16C/6N5) Three-Phase PWM Control Register NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Rewrite bits INV00 to ...
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M16C/6N Group (M16C/6N5) Three-Phase PWM Control Register NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Timers A1, A2, ...
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M16C/6N Group (M16C/6N5) Three-Phase Output Buffer Register NOTE: 1. The values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by ...
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M16C/6N Group (M16C/6N5) Timer Ai, Ai-1 Register ( b15 NOTES: 1. Use a 16-bit data for read and write the TAi or TAi1 register is set to 0000h, no counters start ...
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M16C/6N Group (M16C/6N5) Timer B2 Interrupt Generation Frequency Set Counter b7 b0 NOTES: 1. Use the MOV instruction to set the ICTB2 register the INV01 bit is set to 1, set the ICTB2 register when the TB2S bit ...
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M16C/6N Group (M16C/6N5) Trigger Select Register NOTES: 1. Set the corresponding port direction bit to 0 (input mode). 2. Overflow or underflow. Count Start Flag ...
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M16C/6N Group (M16C/6N5) Timer Ai Mode Register ( NOTE: 1. Selected by the PCLK0 bit in the PCLKR register. Timer B2 Mode ...
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M16C/6N Group (M16C/6N5) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1, ...
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M16C/6N Group (M16C/6N5) Sawtooth waveform as a carrier wave Sawtooth wave Signal wave Timer B2 Timer A4 start (1) trigger signal Timer A4 one-shot (1) pulse U-Phase output (1) signal U-Phase output (1) signal U-phase INV14 = 0 ("L" active) ...
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M16C/6N Group (M16C/6N5) 15. Serial Interface Serial interface is configured with 4 channels: UART0 to UART2 and SI/O3. 15.1 UARTi ( UARTi each have an exclusive timer to generate a transfer clock, so they operate independently ...
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M16C/6N Group (M16C/6N5) Main clock, PLL clock, or on-chip oscillator clock (UART0) RXD polarity RXD0 reversing circuit Clock source selection CLK1 to CLK0 CKDIR 00h Internal f1SIO or f2SIO 01h 0 f8SIO 10h f32SIO 1 External CKPOL CLK polarity CLK0 ...
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M16C/6N Group (M16C/6N5) Main clock, PLL clock, or on-chip oscillator clock (UART2) RXD polarity reversing RXD2 circuit Clock source selection CLK1 to CLK0 CKDIR 00 Internal f1SIO or f2SIO 01 0 f8SIO 10 f32SIO 1 External Clock synchronous type CKPOL ...
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M16C/6N Group (M16C/6N5) IOPOL No reverse RXDi 0 RXD data reverse circuit 1 Reverse STPS 1SP PAR 1 2SP PRYE STPS PAR 2SP enabled PAR 0 1SP PAR disabled i = ...
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M16C/6N Group (M16C/6N5) UARTi Transmit Buffer Register ( (b15) (b8 NOTE: 1. Use the MOV instruction to write to this register. UARTi Receive Buffer Register ( (b15) (b8) b7 ...
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M16C/6N Group (M16C/6N5) UARTi Transmit/Receive Mode Register ( NOTES receive data, set the corresponding port direction bit for each RXDi pin to 0 (input mode). 2. Set ...
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M16C/6N Group (M16C/6N5) UARTj Transmit/Receive Control Register NOTE: 1. The UjLCH bit is enabled when bits SMD2 to SMD0 in the UjMR register are set to 001b ...
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M16C/6N Group (M16C/6N5) UART Transmit/Receive Control Register NOTE: 1. When using multiple transfer clock output pins, make sure the following conditions are met: The CKDIR bit in the U1MR register = ...
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M16C/6N Group (M16C/6N5) UARTi Special Mode Register UARTi Special Mode Register NOTES: ...
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M16C/6N Group (M16C/6N5) UARTi Special Mode Register NOTE: 1. Set to 0 when each condition is generated. Figure 15.10 Registers U0SMR4 to U2SMR4 Rev.2.40 Apr 14, ...
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M16C/6N Group (M16C/6N5) 15.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to ...
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M16C/6N Group (M16C/6N5) Table 15.2 Registers to be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit (1) UiTB (1) UiRB OER UiBRG (1) UiMR SMD2 to SMD0 CKDIR ...
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M16C/6N Group (M16C/6N5) Table 15.3 lists the I/O Pin Functions (when not select multiple transfer clock output pin select function) in clock synchronous serial I/O mode. Table 15.4 lists the P6_4 Pin Functions in clock synchronous serial I/O mode. Note ...
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M16C/6N Group (M16C/6N5) (1) Example of transmit timing (when internal clock is selected) Transfer clock 1 TE bit in 0 Data is set to the UiTB register UiC1 register 1 TI bit in UiC1 register 0 "H" CTSi "L" CLK ...
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M16C/6N Group (M16C/6N5) 15.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. • Resetting the UiRB register ( (1) ...
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M16C/6N Group (M16C/6N5) 15.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register ( select the transfer format. Figure 15.13 shows the Transfer Format. (1) When the UFORM bit in the ...
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M16C/6N Group (M16C/6N5) 15.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register ( (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, ...
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M16C/6N Group (M16C/6N5) _______ _______ 15.1.1.7 CTS/RTS Function _______ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi ( pin. Transmit and receive operation begins when the ...
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M16C/6N Group (M16C/6N5) 15.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 15.5 lists the UART Mode Specifications. Table 15.6 lists the Registers ...
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M16C/6N Group (M16C/6N5) Table 15.6 Registers to Be Used and Settings in UART Mode Register Bit UiTB UiRB OER,FER,PER,SUM Error flag UiBRG UiMR SMD2 to SMD0 CKDIR STPS PRY, PRYE IOPOL ...
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M16C/6N Group (M16C/6N5) Table 15.7 lists the I/O Pins Functions in UART mode. Table 15.8 lists the P6_4 Pin Functions in UART mode. Note that for a period from when the UARTi operating mode is selected to when transfer starts, ...
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M16C/6N Group (M16C/6N5) (1) 8-bit data transmit timing (with a parity and 1 stop bit) Transfer Clock 1 TE bit in UiC1 register bit in UiC1 register 0 "H" CTSi "L" Start bit TXDi ST 1 TXEPT ...
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M16C/6N Group (M16C/6N5) • Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit) UiBRG count source 1 RE bit in UiC1 register 0 RXDi Transfer clock Reception triggered when transfer clock 1 is generated ...
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M16C/6N Group (M16C/6N5) 15.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below. • Resetting the UiRB register ( (1) Set the RE ...
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M16C/6N Group (M16C/6N5) 15.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 15.20 shows ...
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M16C/6N Group (M16C/6N5) _______ _______ 15.1.2.6 CTS/RTS Function _______ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi ( pin. Transmit operation begins when the CTSi/RTSi pin is held ...
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M16C/6N Group (M16C/6N5) 15.1.3 Special Mode mode is provided for use as a simplified I Specifications. Figure 15.23 shows the I 2 Used and Setting Mode. Table 15.12 lists the I to ...
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M16C/6N Group (M16C/6N5) SDAi Delay circuit ACKC=1 ACKD bit Noise Filter Falling edge detection SCLi IICM=0 UARTi IICM=1 Noise Filter This diagram applies to the case where bits SMD2 to SMD0 in the UiMR register = 010b and the IICM ...
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M16C/6N Group (M16C/6N5) Table 15.11 Registers to Be Used and Settings in I Register Bit UiTB ( UiRB ( ABT OER UiBRG UiMR (1) SMD2 to SMD0 CKDIR IOPOL UiC0 ...
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M16C/6N Group (M16C/6N5) 2 Table 15. Mode Functions Clock Synchronous Serial I/O Mode Function (SMD2 to SMD0 = 001b, IICM = 0) Source of interrupt - number 6, 7, and (1) (5) (7) 10 Source of interrupt UARTi ...
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M16C/6N Group (M16C/6N5) (1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay) 1st bit 2nd bit SCLi D7 D6 SDAi (2) IICM2 = 0, CKPH = 1 (clock delay) 1st bit 2nd bit SCLi D7 ...
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M16C/6N Group (M16C/6N5) 15.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while ...
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M16C/6N Group (M16C/6N5) Table 15.13 STSPSEL Bit Functions Function Output of pins SCLi and SDAi Start/stop condition interrupt request generation timing (1) When slave CKDIR bit = 1 (external clock) STSPSEL bit 0 SCLi SDAi (2) When master CKDIR bit ...
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M16C/6N Group (M16C/6N5) 15.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 15.24 Transfer to UiRB Register and Interrupt Timing. The CSC bit in the UiSMR2 register is used to synchronize the internally ...
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M16C/6N Group (M16C/6N5) 15.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), ...
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M16C/6N Group (M16C/6N5) 15.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 15.14 lists the Special Mode 2 Specifications. Figure 15.27 shows the Serial Bus Communication Control Example ...
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M16C/6N Group (M16C/6N5) Figure 15.27 Serial Bus Communication Control Example (UART2) Rev.2.40 Apr 14, 2006 page 172 of 372 REJ09B0011-0240 P1_3 P1_2 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (Master) 15. Serial Interface P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) MCU (Slave) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) ...
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M16C/6N Group (M16C/6N5) Table 15.15 Registers to Be Used and Settings in Special Mode 2 Register Bit (1) UiTB (1) UiRB OER UiBRG (1) UiMR SMD2 to SMD0 CKDIR IOPOL UiC0 ...
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M16C/6N Group (M16C/6N5) 15.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the ...
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M16C/6N Group (M16C/6N5) "H" Slave control input "L" "H" Clock input "L" (CKPOL= 0, CKPH = 0) Clock input "H" (CKPOL = 1, CKPH = 0) "L" "H" Data output timing "L" Data input timing Figure 15.29 Transmission and Reception ...
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M16C/6N Group (M16C/6N5) 15.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 15.16 lists the Registers to be Used and Settings in IE mode. Figure 15.31 ...
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M16C/6N Group (M16C/6N5) (1) The ABSCS bit in UiSMR register (bus collision detect sampling clock select) If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock Transfer clock TXDi RXDi Timer Aj timer ...
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M16C/6N Group (M16C/6N5) 15.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin ...