M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 144
M306N5FCTFP
Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N5FCTFPUK.pdf
(90 pages)
3.M306N5FCTFPU0.pdf
(408 pages)
Specifications of M306N5FCTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Table 13.8 Pulse Period and Pulse Width Measurement Mode Specifications
i = 0 to 5
NOTES:
Count source
Count operation
Count start condition
Count stop condition
Interrupt request
generation timing
TBiIN pin function
Read from timer
Write to timer
13.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. Table 13.8 lists the Pulse Period and Pulse Width Measurement Mode Specifications.
Figure 13.20 shows Registers TB0MR to TB5MR in Pulse Period and Pulse Width Measurement mode.
Figure 13.21 shows the Operation Timing when Measuring Pulse Period. Figure 13.22 shows the Operation
Timing when Measuring Pulse Width.
1.Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
2. Interrupt request is not generated when the first effective edge is input after the timer started counting.
3. Value read from the TBi register is undefined until the second valid edge is input after the timer starts
assigned to bits 5 to 7 in the TBSR register.
counting.
Apr 14, 2006
Item
page 122 of 372
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of
Set the TBiS bit
Set the TBiS bit to 0 (count stops)
• When an effective edge of measurement pulse is input
• Timer overflow. If an overflow occurs, the MR3 bit in the TBiMR register
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading
TBi register
Value written to the TBi register is written to neither reload register nor counter
measurement pulse. The counter value is set to 0000h to continue counting.
is set to 1 (overflow) simultaneously. The MR3 bit is set to 0 (no overflow)
by writing to the TBiMR register at the next count timing or later after the
MR3 bit was set to 1. At this time, make sure the TBiS bit is set to 1
(count starts).
(3)
(1)
to 1 (count starts)
Specification
(2)
13. Timers
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