M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 380

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
23.11 CAN Module
Table 23.2 CAN Module Status Updating Period
(Example 1) Condition XIN 16 MHz CCLK: Divide-by-1
(Example 2) Condition XIN 16 MHz CCLK: Divide-by-2
(Example 3) Condition XIN 16 MHz CCLK: Divide-by-4
(Example 4) Condition XIN 16 MHz CCLK: Divide-by-8
(Example 5) Condition XIN 16 MHz CCLK: Divide-by-16
23.11.1 Reading C0STR Register
The CAN module on the M16C/6N Group (M16C/6N5) updates the status of the C0STR register in a
certain period. When the CPU and the CAN module access to the C0STR register at the same time, the
CPU has the access priority; the access from the CAN module is disabled. Consequently, when the
updating period of the CAN module matches the access period from the CPU, the status of the CAN
module cannot be updated. (See Figure 23.3 When Updating Period of CAN Module Matches Access
Period from CPU.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(a) There should be a wait time of 3fCAN or longer (see Table 23.2 CAN Module Status Updating
(b) When the CPU polls the C0STR register, the polling period must be 3 fCAN or longer. (See Figure 23.5
3fCAN Period = 3
Period) before the CPU reads the C0STR register. (See Figure 23.4 With Wait Time of 3 fCAN
before CPU Read.)
When Polling Period of CPU is 3 fCAN or Longer.)
Apr 14, 2006
page 358 of 372
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XIN (Original Oscillation Period)
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3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
3 fCAN period = 3
Division Value of CAN Clock (CCLK)
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62.5 ns
62.5 ns
62.5 ns
62.5 ns
62.5 ns
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23. Usage Notes
1 = 187.5 ns
2 = 375 ns
4 = 750 ns
8 = 1.5 µs
16 = 3 µs