M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 126

IC M16C MCU FLASH 100QFP

M306N5FCTFP

Manufacturer Part Number
M306N5FCTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets

Specifications of M306N5FCTFP

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M16C/6N Group (M16C/6N5)
Rev.2.40
REJ09B0011-0240
Figure 13.5 Registers TABSR and UDF
Count Start Flag
Up/Down Flag
NOTES:
b7
b7
1.Use the MOV instruction to write to this register.
2.Make sure the port direction bits for pins TA2IN to TA4IN, and TA2OUT to TA4OUT are set to 0
3.When not using the two-phase pulse signal processing function, set the corresponding bit to timers
Apr 14, 2006
b6
b6
(input mode).
A2 to A4 to 0.
b5
b5
b4
b4
b3
b3
b2
b2
page 104 of 372
(1)
b1
b1
b0
b0
Bit Symbol
Bit Symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
TA2P
TA3P
TA4P
Symbol
TABSR
Symbol
UDF
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Timer A0 up/down flag
Timer A1 up/down flag
Timer A2 up/down flag
Timer A3 up/down flag
Timer A4 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Address
0380h
Address
Bit Name
Bit Name
0384h
After Reset
After Reset
0 : Count stops
1 : Count starts
0 : Down count
1 : Up count
Enabled by setting the MR2 bit in
the TAiMR register to 0
(= switching source in UDF register)
during event counter mode.
0 : Two-phase pulse signal
1 : Two-phase pulse signal
00h
00h
processing disabled
processing enabled
Function
Function
(2) (3)
WO
WO
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
13. Timers

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