MC9S08RD32CPE Freescale Semiconductor, MC9S08RD32CPE Datasheet - Page 72

• Manufacturer Part Number: MC9S08RD32CPE
• Description: IC MCU 32K FLASH 2K RAM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CPE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Resets, Interrupts, and System Configuration
5.8.8
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
1. LVWF will be set in the case when V
72
LVWACK
PPDACK
PPDC
LVWF
PPDF
Field
PDC
7
6
3
2
1
0
Reset
W
R
System Power Management Status and Control 2 Register
(SPMSC2)
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
Partial Power Down Acknowledge — Writing a logic 1 to PPDACK clears the PPDF bit.
Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.
LVWF
0
7
(1)
= Unimplemented or Reserved
LVWACK
6
0
0
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Supply
Table 5-11. SPMSC2 Field Descriptions
transitions below the trip point or after reset and V
0
0
5
4
0
0
Description
PPDF
0
3
PPDACK
2
0
0
Supply
Freescale Semiconductor
is already below V
PDC
0
1
PPDC
0
0
LVW
.