R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1025
![IC SUPERH MPU ROMLESS 240QFP](/photos/28/62/286223/240-bfqfp__prqp0240kc-a_sml.jpg)
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 19.15 shows allowed state transitions.
Notes: 1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if
The following table shows conditions to access registers.
⎯ Please don't set MCR5 (Sleep Mode) without entering Halt Mode.
⎯ After MCR1 is set, please don't clear it before GSR4 is set and RCAN-TL1 enters Halt
Mode.
2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by
3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically
4. When MCR5 is cleared and MCR1 is set at the same time, RCAN-TL1 moves to Halt
MCR7 is set or by writing ‘0’.
the same instruction.
in HW when RCAN-TL1 moves to Bus Off and MCR14 and MCR6 are both set.
Request. Right after that, it moves to Halt Mode with no reception/transmission.
clear MCR1
and MCR5
except Transmitter/Receiver/BusOff, if MCR6 = 0
BusOff or except Transmitter/Receiver, if MCR6 = 1
set MCR1*
Halt Request
Halt Mode
Figure 19.15 Halt Mode/Sleep Mode
3
Transmission
clear MCR1*
Reception
set MCR5
Reset
Power On/SW Reset
clear MCR0
and GSR3 = 0
Section 19 Controller Area Network (RCAN-TL1)
2
clear MCR5
set MCR1*
Rev. 3.00 Sep. 28, 2009 Page 993 of 1650
clear MCR5*
Sleep Mode
4
1
REJ09B0313-0300
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