R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1394
![IC SUPERH MPU ROMLESS 240QFP](/photos/28/62/286223/240-bfqfp__prqp0240kc-a_sml.jpg)
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 25 Pin Function Controller (PFC)
Table 25.8 Selection of the Source of Oversampling Clock by Setting the SSInCKS Bits
Notes: 1. n = 0 to 3
Rev. 3.00 Sep. 28, 2009 Page 1362 of 1650
REJ09B0313-0300
Bit
2 to 0
Settings of
SSInCKS[2:0]*
000
001
010
011
100
101
110
111
2. When using the AUDIO_CLK input clock, set the PF30MD0 bit of the port F control
Bit Name
SSI0CKS
[2:0]
register H4 (PFCRH4) to 1.
1
Initial
Value
000
0 or 1
AUDIO_X1 input
AUDIO_X1 input/4
AUDIO_CLK input*
AUDIO_CLK input*
EXTAL input
EXTAL input/4
EXTAL input/2
EXTAL input/8
R/W
R/W
Description
SSI ch0 Clock Select
Select the source of the oversampling clock that is
used in channel 0 of the SSI. For settings, see table
25.8.
2
2
/4
Clock Operation Mode
2
CKIO input
CKIO input/4
CKIO input/2
CKIO input/8
3
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
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