R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 735

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

14.3.9
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the
RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From
among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and
alarm register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
The assignable range is from 00 through 59 + ENB bits (practically in BCD), otherwise operation
errors occur.
Bit
7
6 to 4
3 to 0
Bit Name
ENB
10 seconds Undefined R/W
1 second
Second Alarm Register (RSECAR)
Initial value:
Initial
Value
Undefined R/W
0
R/W:
BIt:
ENB
R/W
7
0
R/W
R/W
R/W
6
-
10 seconds
Description
When this bit is set to 1, a comparison with the
Ten's position of seconds setting value
One's position of seconds setting value
RSECCNT value is performed.
R/W
5
-
R/W
4
-
R/W
3
-
Rev. 3.00 Sep. 28, 2009 Page 703 of 1650
R/W
1 second
2
-
R/W
1
-
Section 14 Realtime Clock (RTC)
R/W
0
-
REJ09B0313-0300