R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1463

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

• Canceling by an interrupt
• Canceling with a reset
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0 assigned to PE11 to PE4) (selected by the
IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the
interrupt controller (INTC)) is detected, clock oscillation is started after the wait time for the
oscillation settling time. After the oscillation settling time has elapsed, deep standby mode is
cancelled and the power-on reset exception handling is executed. If the priority level of the
generated interrupt is equal to or lower than the interrupt mask level specified in the status
register (SR) of the CPU, the interrupt request is not accepted and deep standby mode is not
canceled.
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until deep standby mode is canceled. When deep standby mode is canceled by the
falling edge of the NMI pin, the NMI pin should be high when the CPU enters deep standby
mode (when the clock pulse stops) and should be low when deep standby mode is canceled
(when the clock is initiated after oscillation settling). When deep standby mode is canceled by
the rising edge of the NMI pin, the NMI pin should be low when the CPU enters deep standby
mode (when the clock pulse stops) and should be high when deep standby mode is canceled
(when the clock is initiated after oscillation settling). (The same applies to the IRQ pin.)
In addition, the pin levels of the NMI pin and all interrupt pins (IRQ) selected to cancel deep
standby mode (by settings in the deep standby mode cancelation source select register) should
be as follows during the transition to deep standby mode, regardless of whether or not those
pins are actually used to cancel deep standby mode:
⎯ Pins set to cancel deep standby mode at their rising edge should be low during the
⎯ Pins set to cancel deep standby mode at their falling edge should be high during the
When the RES pin is driven low, this LSI leaves deep standby mode and enters the power-on
reset state. After this, driving the RES pin high initiates power-on reset exception handling.
Driving the RES pin low in clock mode 0, 1, or 3 starts output of the internal clock from the
CKIO pin.
Driving the MRES pin low cancels deep standby mode and causes a transition to the power-on
reset state. After this, driving the MRES pin high initiates power-on reset exception handling.
In clock mode 0, 1, or 3, output of the internal clock from the CKIO pin also starts by driving
the MRES pin high.
Keep the RES or MRES pin low until the clock oscillation has settled.
transition.
transition.
Rev. 3.00 Sep. 28, 2009 Page 1431 of 1650
Section 28 Power-Down Modes
REJ09B0313-0300