MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 48

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resets, Interrupts, and Low-Power Modes
The sequence for resetting the watchdog timer is:
Both writes must occur in this sequence prior to the timeout, but any number of instructions can be
executed between the two writes.
4.2.4 Clock Monitor Reset
The MCU contains a clock monitor circuit that measures the E-clock frequency. If the E-clock input rate
is above approximately 200 kHz, then the clock monitor does not generate an MCU reset. If the E-clock
signal is lost or its frequency falls below 10 kHz, then an MCU reset can be generated, and the RESET
pin is driven low to reset the external system.
4.2.5 System Configuration Options Register
The system configuration options register (OPTION) is a special-purpose register with several
time-protected bits. OPTION is used during initialization to configure internal system options.
Bits 5, 4, 2, 1, and 0 can be written only once during the first 64 E-clock cycles after reset in normal modes
(where the HPRIO register bit (SMOD) is cleared). In special modes (where SMOD = 1), the bits can be
written at any time. Bit 3 can be written at anytime.
48
1. Write $55 to the COP reset register (COPRST) to arm the COP timer clearing mechanism.
2. Write $AA to the COPRST register to clear the COP timer
CR0 CR1
0
0
1
1
Address:
Reset:
Read:
Write:
0
1
0
1
Figure 4-1. Arm/Reset COP Timer Circuitry Register (COPRST)
Divided
$003A
E ÷ 2
Bit 7
Bit 7
E =
0
By
16
64
1
4
15
–0/+15.6 ms
XTAL = 2
15.625 ms
Bit 6
Time Out
2.1 MHz
62.5 ms
250 ms
6
0
1 sec
Table 4-1. COP Time Out Periods
MC68HC711D3 Data Sheet, Rev. 2.1
23
Bit 5
5
0
–0/+16.4 ms
16.384 ms
65.536 ms
262.14 ms
Time Out
1.049 sec
8.0 MHz
2.0 MHz
XTAL =
Bit 4
4
0
–0/+26.7 ms
4.9152 MHz
1.2288 MHz
26.667 ms
106.67 ms
426.67 ms
Time Out
1.707 sec
XTAL =
Bit 3
3
0
Bit 2
–0/+32.8 ms
2
0
131.07 ms
524.29 ms
32.768 ms
Time Out
4.0 MHz
1.0 MHz
XTAL =
2.1 sec
Bit 1
1
0
–0/+35.6 ms
3.6864 MHz
35.556 ms
142.22 ms
568.89 ms
921.6 kHz
Time Out
2.276 ms
Freescale Semiconductor
XTAL =
Bit 0
Bit 0
0