MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 91

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Compare (OC)
8.4 Output Compare (OC)
Use the output compare (OC) function to program an action to occur at a specific time — when the 16-bit
counter reaches a specified value. For each of the five output compare functions, there is a separate
16-bit compare register and a dedicated 16-bit comparator. The value in the compare register is
compared to the value of the free-running counter on every bus cycle. When the compare register
matches the counter value, an output compare status flag is set. The flag can be used to initiate the
automatic actions for that output compare function.
To produce a pulse of a specific duration, write to the output compare register a value representing the
time the leading edge of the pulse is to occur. The output compare circuit is configured to set the
appropriate output either high or low, depending on the polarity of the pulse being produced. After a match
occurs, the output compare register is reprogrammed to change the output pin back to its inactive level
at the next match. A value representing the width of the pulse is added to the original value, and then is
written to the output compare register. Because the pin state changes occur at specific values of the
free-running counter, the pulse width can be controlled accurately at the resolution of the free-running
counter, independent of software latencies. To generate an output signal of a specific frequency and duty
cycle, repeat this pulse-generating procedure.
There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and TOC4, and the
TI4/O5 register, which functions under software control as either IC4 or OC5. Each of the OC registers is
set to $FFFF on reset. A value written to an OC register is compared to the free-running counter value
during each E-clock cycle. If a match is found, the particular output compare flag is set in timer interrupt
flag register 1 (TFLG1). If that particular interrupt is enabled in the timer interrupt mask register 1
(TMSK1), an interrupt is generated. In addition to an interrupt, a specified action can be initiated at one
or more timer output pins. For OC5–OC2, the pin action is controlled by pairs of bits (OMx and OLx) in
the TCTL1 register. The output action is taken on each successful compare, regardless of whether the
OCxF flag in the TFLG1 register was previously cleared.
OC1 is different from the other output compares in that a successful OC1 compare can affect any or all
five of the OC pins. The OC1 output action taken when a match is found is controlled by two 8-bit registers
with three bits unimplemented: the output compare 1 mask register, OC1M, and the output compare 1
data register, OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies what data
is placed on these port pins.
8.4.1 Timer Output Compare Registers
All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset. If an output
compare register is not used for an output compare function, it can be used as a storage location. A write
to the high-order byte of an output compare register pair inhibits the output compare function for one bus
cycle. This inhibition prevents inappropriate subsequent comparisons. Coherency requires a complete
16-bit read or write. However, if coherency is not needed, byte accesses can be used.
For output compare functions, write a comparison value to output compare registers TOC1–TOC4 and
TI4/O5. When TCNT value matches the comparison value, specified pin actions occur.
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
91